Gaming PC

AMD Instinct MI300 Data Center APU Pictured Up Close: 13 Chiplets, 146 Billion Transistors

(Image credit: Marco Chiapetta)

AMD unveiled its next-generation Instinct MI300 accelerator at CES 2023. We were lucky enough to get some hands-on time and take some close-up images of the mammoth chip.

Without a doubt, the Instinct MI300 is a groundbreaking design. The data center APU blends a total of 13 chiplets, many of which are 3D stacked to create a chip with 24 Zen 4 CPU cores fused with CDNA 3 graphics. 8 stacks of engines and HBM3. All in all, this chip features his 146 billion transistors, making it the largest chip AMD has put into production.

The MI300 has a total transistor count of 146 billion, easily beating Intel’s 100 billion transistor Ponte Vecchio combined with 128 GB of HBM3 memory. The stripped chip is very difficult to photograph given its shiny appearance, but you can clearly see his eight stacks of HBM3 flanking the center die. A small sliver of structural silicon is placed between these HBM stacks to ensure stability when the cooling solution is torqued onto the package.

The computing portion of the chip is made up of nine 5nm chiplets which are either CPU or GPU cores but AMD has not provided details on how many of each will be used. Zen 4 cores will typically roll out as an 8-core die, so we can consider 3 CPU dies and 6 GPU dies. The GPU die uses AMD’s CDNA 3 architecture. This is his third revision of AMD’s data center-specific graphics architecture. AMD did not specify his CU count.

These nine dies are 3D stacked on top of four 6nm-based dies that are more than just passive interposers. These dies are said to be active and handle I/O and various other functions. An AMD rep showed us another MI300 sample of his. In this sample, the top die was sanded with a belt sander, revealing four active interposer dies underneath. There, a memory controller that interfaces with the HBM3 stack, as well as communication between I/O tiles. This second sample of his could not be filmed.

The 3D design enables incredible data throughput between the CPU, GPU, and memory dies while also allowing the CPU and GPU to operate on the same data in memory simultaneously (zero-copy), saving power and improving performance. improves and simplifies programming. It will be interesting to see if this device can be used without standard his DRAM as seen with Intel’s Xeon Max CPU which employs on-package HBM.

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