AMD announced its RDNA 3 architecture in June, but the chipmaker declined to share specifications on its next-generation graphics cards. but, Anglonomics (opens in new tab) We have shared some new information about AMD’s latest Navi 3x silicon. The new outlet claims the specs were finalized in 2020 and no changes have been made since then.
Angstronomics details three Navi 3x silicons: Navi 31, Navi 32 and Navi 33. Navi 31 is the flagship silicon and is touted as the world’s first GPU with a chiplet design. The Navi 31 with the GFX1100 ID (codename Plum Bonito) will reportedly feature 1 Graphics Chiplet Die (GCD) and 6 Memory Chiplet Dies (MCD). The publication believes that GCD is on TSMC’s 5nm process node and MCD is a product of his 6nm process node.
The approximately 308 mm² GCD houses up to 48 Workgroup Processors (WGPs). Breaking this down means that each WGP has 2 Compute Units (CUs) and the Navi 31 die features 96 CUs or 12,288 ALUs. On the other hand, the size of MCD is about 37.5 mm². Each MCD has 16MB of AMD’s infinity cache, so a Navi 31 powered graphics card can use up to 96MB of infinity cache. Navi 31 comes with a 384-bit memory interface. Navi 31’s Infinity Cache is smaller than Navi 21 which has 128MB Infinity Cache. Angstronomics believes AMD is preparing a 3D stacked MCD (1-hi) that doubles the Infinity Cache. Nonetheless, given the increased cost, performance gains are not substations, so the mainstream Navi 31 sticks with 96MB. It was previously included in AMD’s plans, but the chip maker may have scrapped it due to its terrible profit-to-cost ratio.
According to information from Angstronomics, AMD may offer a cutdown version of the Navi 31 SKU. The lower variant may arrive with only 42 WGPs (84 CUs or 10,752 ALUs). The silicon is said to have one less MCD and max out with an 80MB infinity cache configuration and a 320-bit memory bus.
Barring any changes, the Navi 31 based reference design appears to feature an updated triple-fan cooling system that is moderately taller than the existing Navi 21 design. The transformation also includes his three red stripe accents on the heatsink fins. As for power requirements, the Navi 31 can be served with just two 8-pin PCIe power connectors.
AMD RDNA 3 Spec*
|Navi 31||Navi 32||Navi 33|
|code name||plum bonito||wheat eggplant||hot pink bonefish|
|design||Chiplets: 1x GCD, 6x MCD||Chiplets: 1x GCD, 4x MCD||Monolithic (TSMC N6, ~203 mm²)|
|GCD||TSMC N5, ~308mm²||TSMC N5, ~200mm²||none|
|MCD||TSMC N6, ~37.5mm²||TSMC N6, ~37.5mm²||none|
|Infinity Cache (MB)||96||64||32|
|memory interface||384 bits||256 bits||128 bit|
*Specifications are unconfirmed.
Navi 32, aka GFX1101 (codenamed Wheat Nas), is a smaller version of Navi 31, targeting both mobile and desktop segments. The GCD and MCD sizes are 200 mm² and 37.5 mm² respectively. GCD has only 30 WGPs, which amounts to a maximum of 60 CUs (7,680 ALUs). Since Navi 32 only has 4 MCDs, the Infinity cache is limited to 64MB. Again, smaller than the Navi 22’s 96MB configuration. Angstronomics believes AMD has considered his 128MB (1-hi) variant for his Navi 32. The advantage may not justify the higher cost, so the model may not hit the market.
In contrast, the Navi 33, GFX1102 (Hotpink Bonefish) sticks to a monolithic design, with a die size of around 203 mm². According to a report by Angstronomics, AMD was planning to make the Navi 33 a chiplet die with 18 WGPs and 2 MCDs. AMD reportedly stuck with a monolithic die as volume and cost fell short of AMD’s goals.
Both mobile and desktop graphics cards display Navi 33. However, AMD’s priority is to push Navi 33 to mobile devices, especially with the AMD Advantage initiative. Laptops are therefore preferred over their desktop counterparts.
Navi 33 has 16 WGPs, which equates to 32 CUs (4,096 ALUs). The Navi 33 boasts drop-in compatibility with the Navi 23 PCB, facilitating cross-vendor adoption. It has 32MB of infinity cache and a 128-bit memory interface. According to Angstronomics, the Navi 33 outperforms Intel’s top-of-the-line Arc Alchemist offering, costing just half the manufacturing cost and being more power efficient.