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Imec Reveals Sub-1nm Transistor Roadmap, 3D-Stacked CMOS 2.0 Plans

Imec, the world’s most advanced semiconductor research company, recently shared its sub-1nm silicon and transistor roadmap at the ITF World event in Antwerp, Belgium. The roadmap provides a timeline through 2036 for the next major process nodes and transistor architectures that the company will research and develop in its labs in collaboration with industry giants such as TSMC, Intel, Samsung and ASML. The company also outlined a move to what it calls CMOS 2.0. This involves splitting the chip’s functional units, such as the L1 and L2 caches, into a more advanced 3D design than today’s chiplet-based approaches.

Note that Imec’s roadmap includes process nodes below “1nm” because 10 Angstroms equals 1nm. Roadmaps show standard FinFET transistors to last down to 3nm, but then move to new gate-all-around (GAA) nanosheet designs, entering mass production in 2024. imec shows a path map to fork sheet designs in 2nm and A7 (0.7nm), followed by breakthrough designs such as his CFET and atomic channel in A5 and A2 respectively.

(Image credit: imec)

Moving to these smaller nodes has become more expensive over time, and chiplets have already superseded the standard approach of building monolithic chips on a single large die. Chiplet-based designs divide the various chip functions into separate dies that are connected together, thus allowing the chip to function as one cohesive unit, albeit with tradeoffs.

Imec’s vision of the CMOS 2.0 paradigm includes dividing chips into even smaller pieces, partitioning cache and memory into their own units with different transistors, and stacking them in 3D arrangements on top of other chip functions. is included. This methodology also relies heavily on a backside power delivery network (BPDN) that routes all power through the backside of the transistors.

Take a closer look at the imec roadmap and the new CMOS 2.0 methodology.

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