Imec, the world’s most advanced semiconductor research company, recently shared its sub-1nm silicon and transistor roadmap at the ITF World event in Antwerp, Belgium. The roadmap provides a timeline through 2036 for the next major process nodes and transistor architectures that the company will research and develop in its labs in collaboration with industry giants such as TSMC, Intel, Samsung and ASML. The company also outlined a move to what it calls CMOS 2.0. This involves splitting the chip’s functional units, such as the L1 and L2 caches, into a more advanced 3D design than today’s chiplet-based approaches.
Note that Imec’s roadmap includes process nodes below “1nm” because 10 Angstroms equals 1nm. Roadmaps show standard FinFET transistors to last down to 3nm, but then move to new gate-all-around (GAA) nanosheet designs, entering mass production in 2024. imec shows a path map to fork sheet designs in 2nm and A7 (0.7nm), followed by breakthrough designs such as his CFET and atomic channel in A5 and A2 respectively.
Moving to these smaller nodes has become more expensive over time, and chiplets have already superseded the standard approach of building monolithic chips on a single large die. Chiplet-based designs divide the various chip functions into separate dies that are connected together, thus allowing the chip to function as one cohesive unit, albeit with tradeoffs.
Imec’s vision of the CMOS 2.0 paradigm includes dividing chips into even smaller pieces, partitioning cache and memory into their own units with different transistors, and stacking them in 3D arrangements on top of other chip functions. is included. This methodology also relies heavily on a backside power delivery network (BPDN) that routes all power through the backside of the transistors.
Take a closer look at the imec roadmap and the new CMOS 2.0 methodology.
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As you can see in the album above, the industry faces seemingly insurmountable challenges as nodes advance, but the demand for more computing power is growing exponentially, especially in machine learning and AI. increase. Meeting that demand was not easy. While power consumption is steadily increasing in high-end chips, costs are skyrocketing. Power scaling remains a challenge as CMOS operating voltages stubbornly refuse to drop below 0.7 volts, and the continued need to scale up to larger chips creates power and cooling challenges. . A completely new solution to avoid.
And while transistor counts continue to double according to the predictable Moore’s Law, other fundamental issues also become increasingly problematic with each new generation of chips. For example, interconnect bandwidth limitations lag far behind the computing power of modern CPUs and GPUs, which is a hindrance. It degrades performance and limits the effectiveness of additional transistors.
imec transistor and process node roadmap
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However, faster and denser transistors are paramount, and the first wave of these transistors will be on the 2nm node debuting in 2024, replacing the triple-gate FinFETs powering major devices today. Emerging in gated-all-around (GAA)/nanosheet devices. -Edge tip. GAA transistors improve transistor density and performance, including faster transistor switching while using the same drive current as multiple fins. Leakage is also significantly reduced as the channel is fully surrounded by the gate, and power or performance can be optimized by adjusting the channel thickness.
We have already seen several chip makers adopt different variations of this transistor technology. Industry leader TSMC will be the last to adopt the new transistor as it plans to introduce its N2 node with GAA in 2025. Intel’s quad-sheet RibbonFET with the ‘Intel 20A’ process node, featuring four stacked nanosheets each fully gated, is expected to debut in 2024. Samsung was the first to manufacture GAA for production shipments, but small quantities of SF3E pipes are not mass-produced by Cleaner Nodes. Instead, the company plans to debut an advanced node for mass production in 2024.
10 Angstroms (A) corresponds to 1 1 nm. So A14 at 1.4nm, A10 at 1nm, and A7 in the 2030 timeframe to enter the sub-1nm era. Note, however, that these metrics often do not match the actual physical dimensions on the chip.
Imec expects forkseat transistors to start at 1nm (A10) and continue to the A7 node (0.7nm). As you can see on the second slide, this design stacks the NMOS and PMOS separately and separates them with a dielectric barrier, which allows for better performance and higher density.
Complementary FET (CFET) transistors, when they first appear with the 1nm node (A10) in 2028, will allow for even smaller footprints and higher density standard cell libraries. Eventually there will be a version of his CFET with atomic channels that will further improve performance and scalability. CFET transistor read more about here, N and PMOS devices stacked on top of each other to allow for higher density. CFETs should mark the end of the scaling of nanosheet devices and the end of the visible roadmap.
However, breaking the barriers of scaling performance, power and density will require other important technologies, which imec assumes will require the new CMOS 2.0 paradigm and co-optimization of system technology (SCTO). I’m here.
STCO and rear power supply
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At the highest level, system technology co-optimization (STCO) advances the design process by modeling the needs of the system and the target application and using that knowledge to make the design decisions necessary to create a chip. You should reconsider. This design approach often “deconstructs” functional units such as power delivery, I/O, cache, etc. that are normally found as part of a monolithic processor, and divides them into separate units with different functions. to optimize each unit for the required performance characteristics. Increasing the variety of transistors also improves cost.
One of the goals of fully decomposing the standard chip design is to partition the cache/memory into separate layers of the 3D stack design (more on this later). However, this requires reducing complexity at the top of the chip stack. Key to this effort is the innovation of back-end-of-line (BEOL) processes focused on wiring transistors together to enable both communication (signaling) and power delivery.
Unlike today’s designs that route power from the top of the chip to the transistors, the backside power distribution network (BPDN) uses TSVs to route all power directly to the backside of the transistors, thus reducing the power delivery to the data transmission interconnect. separate from The usual place on the other side. Separating the power circuits and the interconnects that carry data improves voltage droop and allows faster transistor switching, while allowing for higher signal routing densities on the chip. Signal integrity also benefits as routing is simplified, resistance and capacitance are reduced, and faster routing is possible.
Moving the power delivery network to the bottom of the chip facilitates wafer-to-wafer bonding at the top of the die, freeing up the possibility of stacking logic on top of memory. imec even envisages the possibility of moving other functions to the backside of the wafer, such as global interconnects and clock signals.
Intel has already announced its own version of BPDN technology called PowerVIA, which will debut in 2024 at a 20A node. Intel plans to reveal more details about this technology at his upcoming VLSI event. On the other hand, TSMC has also announced that it will introduce BPDN in its N2P nodes, which it will start mass-producing in 2026, so it will lag behind Intel for quite some time in this technology. Samsung is also rumored to adopt the technology in his 2nm node.
CMOS 2.0: The Road to True 3D Chips
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CMOS 2.0 is the culmination of imec’s vision for future chip design, including full 3D chip design. We’ve already seen memory stacking with AMD’s 2nd Gen 3D V-Cache, stacking L3 memory on top of the processor for more memory capacity, but imec has its own L1, L2 and L3 caches. It is assumed that the tier contains the entire cache hierarchy. It is stacked vertically on its own die, above the transistors that make up the processing core.
Each level of cache is created using the best transistors for the task. This means older nodes for SRAM, but this is becoming more important as SRAM is starting to scale significantly slower. The shrinking scaling of SRAM has led to cache consuming a higher percentage of the die, increasing the cost per MB and discouraging chip makers from using large caches. As such, the cost savings associated with migrating caches to less dense nodes using 3D stacking may require much larger caches than ever before. 3D stacking, if implemented correctly, can also help reduce latency issues with large caches.
These CMOS 2.0 technologies utilize 3D stacking technologies such as wafer-to-wafer hybrid bonding to form direct die-to-die 3D interconnects. Learn more about.
As you can see in the album above, Imec also has a 3D-SOC roadmap outlining the continued shrinking of the interconnects that tie 3D designs together. This will enable higher speed and higher density interconnects in the future. These advances will be realized in the coming years by using newer types of interconnects and processing methods.
About imec
You may not be familiar with the Interuniversity Microelectronics Center (IMEC), but it ranks among the most important companies in the world. Think of imec like Silicon Switzerland. Imec serves as the quiet cornerstone of the industry, linking strong rivals such as AMD, Intel, Nvidia, TSMC and Samsung with chip tool makers such as ASML and Applied Materials, and leading semiconductor software designers such as Cadence and Applied Materials. Synopsys and others, not to mention the company (EDA), are in a non-competitive environment.
This collaboration will allow the two companies to work together to define a roadmap for the next generation of tools and software used to design and manufacture the chips that power the world. A standardized approach is of paramount importance in the face of significant cost and complexity increases in the chip manufacturing process. Cutting-edge chip makers use much of the same equipment sourced from a few important tool makers, so some standardization is required, and avoiding the laws of physics requires research and development that could start a decade earlier. imec’s roadmap provides extensive information. We look forward to the future progress of the semiconductor industry.
