Intel Announces Agilex 7 M-Series FPGAs with R-Tile, PCIe 5.0 and CXL 2.0 Support
intel announced today The company’s Agilex 7 M-series family of field-programmable gate array (FPGA) products doubles its activated 10nm SuperFin manufacturing node. Citing increasing market demand for FPGA solutions as co-processors for networking, data centers, high-performance computing (HPC) cloud computing, and other applications, Intel is committed to greater flexibility than ever before, primarily (due to the inherently programmable nature of FPGAs) and promises high scaling capabilities. Intel’s Agilex 7 FPGA introduces new chiplets as part of its heterogeneous multi-die architecture. R-tileis responsible for providing the latest connectivity technologies i.e. PCIe 5.0 and CXL support with hard-coded IP blocks for hardware acceleration.
The new Heterogeneous R-Tile chiplet is the centerpiece for Intel, earning the title of the only FPGA family with full PCI-SIG 5.0 x16 data rate certification. Xilinx, now under AMD’s umbrella, is another example of his FPGA development company at the cutting edge, so there’s a feeling that Intel has won the race here.
Interestingly, Intel seems to be tightening the separation between FPGA and CPU products. Perhaps it is the result of an early foray into integration. Only Silicon Ghost Stories Remain. AMD seems pretty confident that it has cracked the case. The company seems to be considering incorporating FPGA functionality into its EPYC CPUs as early as this year. Now, that doesn’t make the departures of the two companies firm. AMD may also be looking at chiplet-like integration either vertically via 3D stacking or by embedding his decoupled FGPA-specific IP into a separate chip.
The general idea of FPGAs is their inherent flexibility, allowing developers to rapidly iterate circuit placement and processing blocks to adapt them to the specific workload at hand. More specialized hardware, FPGAs, can be used to accelerate CPU-independent workloads, thereby dedicating precious CPU resources to specific tasks (cloud-based installation). Efficiency (cost of generalized processing power).
Intel’s R-tile essentially embeds a hardware acceleration IP block responsible for handling PCIe 5.0 and CXL 1.1/2.0 protocols into the Agilex 7 FPGA family. This greatly improves power efficiency and data throughput. These are key factors in reducing the total cost of ownership (TCO) of high performance equipment. However, there are always trade-offs between these choices. Intel adds yet another fixed-function hardware block to products that it wants to be programmable. programmable After all, die area is an FPGA buyer’s mantra.
It should also be mentioned that as a product, R-Tile clearly claims that it is “we are here to reduce CPU load while delivering performance gains”. But the other answer to that need is not to move the CPU functions to his FPGA. Simply increase the number of available CPU resources. And it can be done using more CPUs (which might make sense for some installers) or additional CPU cores. After all, Intel’s Agilex 7 M-series are marketed specifically for Intel’s 4th Generation Scalable Xeons, and they aren’t kings of core count in any way.
Intel’s bet is that the above question has an answer, and we know the answer. That’s why we introduced Agilex 7. Intel’s answer is that the consumer wants to eliminate CPU overhead by moving his CPU into his FPGA package. They want the best performance/watt possible (one of the biggest contributors to high TCO costs). So it moves things in the fastest direction. Fortunately, the move benefits Intel in another way. For companies, it is a question of their own efficiency, and therefore of cost.
This is where Intel’s embedded multi-die interconnect bridge (EMIB) comes into play. As the proverbial “glue” that binds disparate processing blocks together, EMIB enables Intel to further isolate IP blocks at the manufacturing level, thereby increasing die efficiency and reducing overall cost per wafer (and resulting cost per chip).
For the consumer, the cost is also theoretically reduced. The dream of Intel (and the industry) is to be able to mix and match different hardware IP blocks (either from the same vendor or from multiple vendors and manufacturing processes). In other words, the customer only has to pay the fee. Check the silicon you actually use and the specs you actually use. In a way, this makes every chip her FPGA.
With all that in mind, the current Agilex 7 with R-Tile could be both a new staple in the Intel Foundry Services (IFS) catalog and a new FPGA offering. Either way, it moves Intel in the direction it wants and needs to go. And it’s just good business.
