Intel today revealed new details about the 3D Foveros chip design it will use for its Meteor Lake, Arrow Lake and Lunar Lake chips as a teaser for the company’s presentation at Hot Chips 34, the semiconductor industry conference that looks at the tech-sharing giants. did. Architectural details of new processors. Intel CEO Pat Gelsinger delivered the event’s keynote, and the company also announced four of his technology presentations, including the consumer-grade “Lake” processors discussed here, Ponte Vecchio GPUs, FPGAs, and Xeon D processors. to hold.
First and foremost, there have been rumors recently that Intel’s Meteor Lake launch to market would be delayed due to Intel switching GPU tiles/chiplets from the TSMC 3nm node to the 5nm node. Intel has not yet shared information about the specific node it will use for the GPU, but a company representative said the planned node for the GPU tile has not changed and the processor is gearing up for an on-time release in 2023. is progressing smoothly.
The first image in the album above is a new diagram Intel has shared of their Meteor Lake processors. Also added the following slides from the Intel 4 process node coverage: The new image contains some new details. According to Intel, this figure is from a mobile processor that will hit the market with 6 performance cores and 2 efficiency core clusters. Although not confirmed by Intel, they are believed to feature the Redwood Cove and Crestmont architectures respectively. Meteor Lake and Arrow Lake chips will scale to meet the needs of the mobile and desktop PC markets, while Lunar Lake will cater to the mobile 15W and below market.
Advances in packaging and interconnects are rapidly changing the face of modern processors. Both are now just as important as the underlying process node technology, and perhaps more important in some respects.
Many of Intel’s disclosures today center around the 3D Foveros packaging technology used as the basis for Meteor Lake, Arrow Lake, and Lunar Lake processors for the consumer market. Chiplets can be vertically stacked on top of a single integrated base die with Intel also uses Foveros in its Ponte Vecchio GPUs, Rialto Bridge GPUs, and Agilex FPGAs, so it’s the underlying technology for several of the company’s next-generation products.
Intel first brought 3D Foveros to market with its low-volume Lakefield processors, but the 4-tile Meteor Lake and nearly 50-tile Ponte Vecchio would be the company’s first high-volume chip production using the technology. After Arrow Lake, Intel will move to the new UCIe interconnect, leveraging a forming ecosystem of chiplets that use standardized interfaces.
Intel has revealed that it will place four Meteor Lake chiplets (called “tiles” in Intel parlance) on top of passive Foveros interposers/base tiles via TSV connections. In other words, the interposer has no logic. The bass style here is different from Lakefield’s, which acted as his SoC of sorts. 3D Foveros technology also supports active interposers. Intel says it manufactures its Foveros interposers on its low-cost, low-power optimized 22FFL process (same as Lakefield). Intel also has a new ‘Intel 16’ variant of this node for foundry services, but it’s not clear which version Intel will use for his Foveros-powered chips.
Intel mounts compute tiles, I/O tiles, SoC tiles, and graphics tiles (tGPU) using the Intel 4 process (more info here) on top of this interposer. All of these units are designed by Intel and feature Intel architecture, while external foundry TSMC manufactures the I/O, SoC, and GPU tiles. This means Intel only manufactures CPUs and Foveros tiles. (Notably, Intel calls his I/O tiles “I/O expanders,” hence the IOE moniker.)
Foveros uses a 36 micron bump pitch (a key measure of interconnect density), while Intel has a roadmap that includes 25 and 18 micron pitches for future designs. Intel says it is theoretically possible to even reach 1 micron bump pitch using Hybrid Bonded Interconnect (HBI) in the future.
Cost was one of the biggest concerns with exotic 3D packaging. Foveros will be Intel’s first product to enter mass production using state-of-the-art packaging technology. However, Intel says chips made in the 3D Foveros package will be very competitively priced with standard monolithic (single die) chip designs, and likely even cheaper.
Intel designed the Foveros die to be the lowest cost possible. This is an order of magnitude cheaper die in the Meteor Lake package and hits the company’s electrical and performance goals. Intel has yet to share the speed and feed of the Foveros interconnect/base tile, but says the interface can run at “multi-GHz” in a passive configuration (this statement is a reference to Intel’s interposer already in development). It also strongly suggests that you have an active version). As such, Foveros has no bandwidth or latency constraints that require design trade-offs. Intel also expects the design to scale well in both performance and cost. This means you can create value-optimized designs or performance-oriented variants for other segments.
However, when you zoom out to the big picture, you can see the real savings. Leading-edge nodes have exponentially higher prices per transistor as the industry moves to smaller nodes, especially for monolithic designs, due to yield issues. Additionally, designing new IP blocks such as I/O interfaces for smaller nodes does not provide much return on investment. So, reusing non-critical tiles/chiplets on “enough” legacy nodes saves time, money and development resources, not to mention simplifying the testing process.
For monolithic dies, Intel has to test various chip elements such as memory and PCIe interfaces in succession. In contrast, Intel can test chiplets simultaneously to save time. Foveros also has an advantage when designing chips for his specific TDP range as he can tailor different chiplets to suit the needs of the design.
If most of these points sound pretty familiar, you’re right. These are the same factors that pushed AMD down the chiplet path in 2017 to great effect. AMD wasn’t the first company to use chiplet-based design, but Intel was a bit behind the technology, as AMD was the first to use the design philosophy to design modern mass-produced chips. , Intel’s first foray into 3D packaging technology is much more complex than AMD’s organic interposer-based design, and has both advantages and disadvantages. The proof is in the final silicon that Intel says is on track for a 2023 launch.
Here’s an overview of the topics Intel will cover at this week’s Hot Chips 34: An update to this article will be coming soon as more detailed coverage will be available once the actual presentation takes place. stay tuned.