Kioxia and WD to Present Details on 3D NAND With 300+ Layers
Kioxia and its research and manufacturing partner Western Digital will unveil innovations enabling high-capacity, high-performance 3D NAND memory devices at the upcoming show. 2023 Symposium on VLSI Technology and CircuitsEngineers from both companies aim to deliver an 8-plane 3D NAND device and a 3D NAND IC with over 300 wordlines. ee news europe.
Eightplane 3D NAND: up to 205 MB/s
As 3D NAND devices increase the number of wordlines, shrink NAND cell dimensions, and increase the capacity of memory ICs, improving read/write performance becomes important. Real devices such as best he SSDs, laptops and smartphones tend to use fewer chips for a given capacity, but end users expect newer devices to be faster than older ones. doing.
One way to improve the performance of 3D NAND ICs is to increase the number of planes to increase internal parallelism. Kioxia presents a paper (C2-1) on an 8-plane 1Tb 3D TLC NAND device with over 210 active layers and a 3.2 GT/s interface. The IC is very similar to Kioxia/Western Digital’s 218-layer 1Tb 3D TLC NAND device with 17Gb/mm^2 density and 3.2 GT/s I/O bus introduced in late March, but this It features 8 planes instead of 4 and is said to deliver 205 MB/s program throughput and 40ms read latency. The specification for the latter is 56ms Kioxia’s 128-layer 3D NAND delivers.
New paper shows Kioxia’s 1Tb 3D TLC NAND device achieves 3.2 GT/s interface speed by reducing data query area in X direction by 41%, speeding up data transfer between memory and host is clarified. However, this new design can lead to routing congestion, which Kioxia has mitigated by introducing the Hybrid Row Address Decoder (X-DEC). X-DEC helps effectively manage increased routing density and minimizes congestion-induced read latency degradation.
Kioxia also implemented a 1-pulse, 2-strobe technique that can detect two memory cells within one pulse, reducing overall detection time by 18% and increasing program throughput to 205 MB/s. The device’s new 8-plane architecture, 1-pulse 2-strobe scheme, and 3.2 GT/s I/O enable 40 ms read latency and 205 MB/s program throughput.
1Tb 3D TLC NAND devices are likely already implementing hybrid row address decoders and 1-pulse 2-strobe techniques for high-speed interfaces, and these techniques could be widely used in the future. However, implementing an 8-plane architecture increases the complexity of both the 3D NAND IC and the supporting memory controller, resulting in higher development and manufacturing costs and longer time-to-market. Additionally, if the host controller fails to properly manage the 8-plane device, the actual performance of the IC may suffer.
>300 layer 3D NAND
In addition to investigating 8-plane 3D NAND IC device structures, Kioxia and Western Digital are also collaborating to develop 3D NAND devices with over 300 active word layers. This increases the vertical channel length and improves the crystalline quality of the channel.
To achieve this, the companies plan to employ metal-induced lateral crystallization (MILC) technology, as described in the T7-1 paper. Using MILC, developers were able to create a 14-micron-long “macaroni-like” silicon (Si) channel mono-crystallized within a vertical memory hole, albeit in a 112-layer prototype device. was made.
This experimental 3D NAND IC is also reported to utilize state-of-the-art nickel gettering methods to remove impurities and defects from the silicon material to improve cell array performance. The result is a minimum 40% reduction in read noise and a 10x increase in channel conductance without sacrificing cell reliability.
>400 layer 3D NAND
Techniques such as string stacking can now build 3D NAND with hundreds of active layers, but it is time consuming. As a result, device manufacturers and wafer fab tool makers are developing ways to increase the layer count by etching longer (deeper) vertical channels.
Etch tool maker Tokyo Electron has published a paper (T3-2 ) will be announced. of toxic substances.
According to Tokyo Electron, its high-aspect-ratio (HAR) dielectric etch technology employs a cryogenic wafer stage and new gas chemistries to create 10-micron-tall channels with a “superior” etch profile of only 33. Create at 84% in minutes. Reduced carbon footprint.