What appears to be TSMC’s internal slides showing development progress on the N3E process are shared by tech enthusiasts HS Quo (opens in new tab) on Twitter. Recently, there was information from Taiwanese business media that the N3 will enter mass production in his September, but there hasn’t been much information about the N3E’s progress since March.
In a quick recap, TSMC N3E is an “enhanced” version of the N3 process. schedule (opens in new tab) (PDF) One year after N3 for mass production. But Kuo’s new undated slides (add a pinch of salt, please) show that N3E is well on its way to development and is “further than planned.”
This chart shows that N3E SRAM yields are significantly higher than N3, starting about six months earlier than risk production. Today, average yields for 256Mb SRAM are said to be around 80%. It is also impressive that the mobile and HPC test chip yields are around 80%. Finally, the yield-proven ring oscillator performance exceeds 92%.
I wouldn’t be surprised by previous reports that N3E is doing very well. TSMC designed his N3E with an improved process window and slightly lower transistor density. This has the natural benefit of increasing yield. Other advertised benefits of N3E are increased clock speeds and reduced power consumption.
In other recent TSMC 3nm news, Taiwan’s commercial times Contract chip makers may have changed their minds about 3nm production in the US, reports
I know that TSMC is building a 5nm fab in Arizona, but in the past they didn’t want to develop fabs on the leading edge of the process outside of Taiwan. Rumor has it that the passage of the US Chip Act has led to research and pilot investments in his second fab that will produce 3nm semiconductor products. TSMC has not responded to the Times report on his commercial.