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N2P Brings Backside Power Delivery in 2026, N2X Added To Roadmap

At today’s 2023 North American Technology Symposium, TSMC revealed additional details about its plans for its N2 2nm-class production node, expected from 2025-26 onwards. TSMC’s N2 fabrication technology family expands with additional variants such as N2P with backside power delivery and his N2X for high-performance computing. Between these upcoming N2 generation process nodes, TSMC is creating a roadmap to continue its relentless pace of increasing transistor performance efficiency, optimizing power consumption, and increasing transistor density.

N2 becomes denser

TSMC’s first N2 manufacturing process, introduced last year, will be the foundry’s first node to use gate-all-around (GAAFET) transistors, which TSMC calls nanosheet transistors. Advantages of GAAFETs over current FinFET transistors include reduced leakage current (due to the presence of gates on all four sides of the channel) and the ability to tune the channel width for higher performance or lower power consumption .

When it introduced the technology last year, TSMC said it would improve transistor performance by 10% to 15% for the same power and complexity, or reduce power consumption by 25% to 30% for the same clock and transistor count. The company also says that the N2 will offer a “mixed” chip density that is over 15% higher than he N3E. This is an increase from the 10% density increase announced last year.

Today, the company said it is on track to develop its N2 technology and that the node will go into mass production in 2025 (probably late 2025). The company also said that the performance of its Nanosheet GAA transistors has exceeded 80% of its target specification two years before it entered HVM, and the average yield of 256Mb SRAM test ICs has exceeded 50%. also said.

“TSMC nanosheet technology exhibits excellent power efficiency and low Vmin, making it ideal for energy-efficient computing paradigms,” said a TSMC statement.

Advertised PPA improvements for new process technology

Data presented in conference calls, events, press briefings and press releases
Power -30% -25-30% -34% -25-30%
performance +15% +10-15% +18% +10-15%
Chip density* ? ? ~1.3X >1.15X
manufacturing industry
Q2 2022 Second half of 2022 Q2/Q3 2023 Second half of 2025

N2P Will Have Backside Power Delivery in 2026

TSMC’s N2 family has evolved and in 2026 the company plans to introduce N2P manufacturing technology. N2P adding a backside power rail to N2’s Nanosheet GAA transistor.

Backside power delivery aims to decouple I/O and power traces by moving the power rail to the back to address challenges such as higher via resistance at the back-end-of-line (BEOL). This improves transistor performance and reduces power consumption. And the backside power feed eliminates potential interference between data and power connections.

Backside powering is an innovation whose importance cannot be overstated. For years, chipmakers have battled resistance in the chip’s power delivery circuitry. A backside power delivery network (PDN) is yet another way to address them. In addition, decoupling the PDN and data connections also helps reduce area, so N2P is expected to further increase transistor density compared to N2.

As of now, TSMC has not disclosed specific numbers on the performance, power, area (PPA) advantage of N2P over N2. However, I’ve heard from industry sources that the backside power rail alone could provide single-digit power improvements and double-digit transistor density improvements.

TSMC has stated that N2P is expected to be production ready in 2026, so we can speculate that the first N2P-based chips will be available in 2027. They will be able to ship their own 20A process on schedule in 2024.

N2X: more performance

In addition to N2P, the flagship of TSMC’s 2nm process generation, TSMC is also preparing for N2X. This makes the manufacturing process tuned for high-performance computing (HPC) applications such as high-end CPUs that require higher voltages and clocks. The foundry has not outlined the specific advantages of this node compared to N2, N2P, and N3X, but as with all performance-enhancing nodes, the real advantage lies in design technology co-optimization (DTCO). is expected to depend heavily on how well practiced .

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