TSMC revealed additional details about its upcoming N2 and N2P process technology at the European Technology Symposium 2023. Both production nodes were developed with High Performance Computing (HPC) in mind and therefore feature many enhancements specifically designed to improve them. performance. On the other hand, given the emphasis on performance efficiency that most chips aim to improve, low-power applications are also likely to take advantage of TSMC’s N2 node. This is due to the natural increase in performance per watt compared to its predecessor.
“N2 is very well suited for the energy-efficient computing paradigm we are in today,” said Yujun Lee, business development director for TSMC’s Foundry’s High Performance Computing business unit, the company’s European technology Mentioned at Symposium 2023. As shown, the speed and power advantages of his N2 over the N3 are very consistent across the voltage supply range, making it suitable for both low power and high performance applications simultaneously. ”
TSMC’s N2 manufacturing node, the foundry’s first manufacturing node to use nanosheet-gate-all-around (GAAFET) transistors, offers 10-15% better transistor performance at the same power and complexity, or lower power consumption. We promise to reduce it by 25-30%. The clock speed and number of transistors are the same. Power delivery is one of the cornerstones of improving transistor performance, and TSMC’s N2 and N2P manufacturing processes introduce several factors. interconnectionRelated innovations provide additional performance. Additionally, N2P introduces a rear power rail to optimize power delivery and die area.
combat resistance
One of the innovations brought by N2 is the Ultra High Performance Metal-Insulator-Metal (SHPMIM) capacitor that improves power supply stability and facilitates on-chip decoupling. According to TSMC, the new SHPMIM capacitors offer more than double the capacitance density compared to the ultra-high density metal-insulator-metal (SHDMIM) capacitors introduced for HPC several years ago. increased 4X the capacitance compared to the previous generation HDMIM). The new SHPMIM reduces Rs sheet resistance (ohms/square) by 50% compared to SHDMIM and reduces Rc via resistance by 50% compared to SHDMIM.
Yet another way to reduce the resistance of the power distribution network is to redesign the redistribution layer (RDL). TSMC will use copper RDLs from the N2 process technology to replace the current aluminum RDLs. Copper RDL offers a similar RDL pitch but with 30% lower sheet resistance and 60% lower via resistance.
Both SHPMIM and Cu RDL are part of TSMC’s N2 technology, which is projected to be used for high-volume manufacturing (HVM) in late 2025 (probably very late in 2025).
Decoupling power and I/O traces
The use of a backside power delivery network (PDN) is another major improvement featured in N2P. The general benefits of rear power rails are well known. Moving the power rails to the back to separate the I/O traces from the power traces allows the power traces to be thicker, thus reducing back-end-of-line (BEOL) via resistance. ), you can expect better performance and lower power consumption. It also reduces cost by reducing logic area by separating I/O wires from power wires.
At Technology Symposium 2023, the company revealed that the N2P backside PDN can achieve 10% to 12% higher performance with reduced IR droop and improved signaling, and a 10% to 15% reduction in logic area. Of course, such an advantage is more apparent with high-performance CPUs and GPUs with dense power delivery networks, so moving it to the back makes a lot of sense.
Backside PDN is part of TSMC’s N2P manufacturing technology that will be deployed in HVM in late 2026 or early 2027.
