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Samsung to Unveil Refined 3nm and Performance-Enhanced 4nm Nodes at VLSI Symposium

Samsung Foundry plans to elaborate on its second-generation 3nm-class manufacturing technology and performance-enhanced 4nm-class manufacturing process at its next meeting. 2023 Symposium on VLSI Technology and Circuits in Kyoto, Japan. SF3 (3GAP) promises measurable improvements in mobile and SoCs, while SF4X (N4HPC) is specifically designed for the most demanding High Performance Computing (HPC) applications Therefore, both technologies are important for contract chip manufacturers.

2nd Generation 3 nm node with GAA transistors

Samsung’s upcoming SF3 (3GAP) process technology is an enhanced version of the company’s SF3E (3GAE) manufacturing process and relies on second-generation gate-all-around transistors, which the company calls multi-bridge channel field effect transistors ( MBCFET). The node promises additional process optimizations, but the foundry doesn’t want to compare SF3 with his SF3E. Compared to its direct predecessor, SF4 (4LPP, 4nm class, low power plus), SF3 offers 22% performance improvement for the same power and complexity, or 34% power reduction for the same clock and transistor count. claim. 21% reduction in logic area. It is unclear if the company has achieved scaling of SRAM and analog circuits.

In addition, Samsung claims that SF3 will allow even greater design flexibility by varying the nanosheet (NS) channel width of MBCFET devices within the same cell type. Interestingly, variable channel width is a feature of GAA transistors that has been debated for years, so Samsung putting it in the context of SF3 means SF3E doesn’t support it. There is a possibility that

So far, neither the conglomerate’s chip development arm, Samsung LSI, nor any other Samsung Foundry customer has officially introduced a single highly complex processor to be mass-produced on the SF3E/3GAE process technology. In fact, cryptocurrency mining chips appear to be the only publicly recognized application to use the industry’s first 3nm-class manufacturing process. trend forceThis is not particularly surprising since Samsung’s “early” node usage is generally very limited.

By contrast, Samsung’s “plus” technology is typically used by a wide range of customers, so its production could increase further when the company’s SF3 (3GAP) process becomes available sometime in 2024. .

SF4X for ultra-high performance applications

In addition to SF3 designed for a variety of envisioned use cases, Samsung Foundry has launched SF4X (4HPC, 4nm-class high-performance computing) designed for performance-demanding applications such as data center-oriented CPUs and GPUs. ing) are being prepared.

To deal with such a chip, Samsung’s SF4X offers a 10% performance boost and 23% power reduction. Samsung doesn’t explicitly specify which process node that comparison is made for, but presumably this is for his default SF4 (4LPP) manufacturing technology. To achieve this, Samsung redesigned the transistor source and drain after re-evaluating the transistor stress (possibly under high load) and further transistor-level design technique co-optimization (T-DTCO). and introduced a new intermediate line (MOL). ) schema.

With new MOL, SF4X guarantees silicon-proven CPU minimum voltage (Vmin) of 60mV, 10% reduction in off-state current (IDDQ) variation, and high voltage (Vdd) operation above 1V without performance degradation , SRAM process margin improvement.

Samsung’s SF4X will be a rival to TSMC’s N4P and N4X nodes scheduled for 2024 and 2025 respectively. It’s hard to tell which technology offers the best combination of performance, power, transistor density, efficiency and cost based solely on claimed specifications. That said, SF4X will be Samsung’s next node specifically designed with his HPC in mind, so Samsung has (or expects) enough customer demand to make it worth spending time on. means

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