Last week, TSMC released its fourth-quarter and full-year 2022 earnings reports. In addition to confirming that TSMC is wrapping up a very busy and highly profitable year for the world’s top chip fab, the annual net profit was about $34 billion. The status of TSMC’s various fab projects.
The big news announced by TSMC in Q4 2022 is that TSMC has started mass production of chips on its N3 (3nm class) manufacturing technology. The launch of this node will initially be quite slow due to the high design cost and complexity of his N3B implementation at the beginning of the node. As such, we do not expect the world’s largest foundry to contribute significantly to revenue in 2023. The company will invest tens of billions of dollars to expand its manufacturing capacity for N3.
slow ramp first
CC Wei, CEO of TSMC, said: “In 2023, we expect a healthy increase, driven by both HPC and smartphone applications. Customer demand for N3 exceeds our supply capacity, so N3 will reach his 2023 We expect it to be fully utilized.”
Given that TSMC’s 2021 and 2022 capex was primarily focused on expanding its N5 (5nm class) manufacturing capacity, it’s no surprise that the company’s N3 capability is modest. TSMC, on the other hand, does not expect N3 to capture a significant share of revenue by Q3.
In fact, the first foundry believes that N3 nodes (including both baseline N3 and the relaxed N3E, which is expected to enter HVM in the second half of 2023) will account for 4% to 6% of the company’s wafer revenue in 2023. I expect. Still, this would exceed his N5 contribution (around $3.5 billion) in his first two quarters of his HVM in 2020.
“We expect [sizable N3 revenue contribution] Launching in Q3 2023, N3 will contribute a mid-single-digit percentage of total wafer revenue in 2023,” said Wei.
Many analysts believe that the baseline N3 (also known as N3B) will be used exclusively or near exclusively by Apple. Apple is TSMC’s largest customer, willing to adopt cutting-edge nodes before all others, despite the high initial cost. If this assumption is correct and Apple is indeed the primary customer with the baseline N3, then it’s worth noting that TSMC is referring to both smartphones and HPC in conjunction with the N3 in 2023. automotive, communications, and smartphone) applications.
N3E comes late
One of the reasons many companies are waiting for TSMC’s relaxed N3E technology (which TSMC says will hit HVM in the second half of 2023) is higher performance and power, as well as aggressive logic scaling. . Another reason is that although the process costs less, it costs less. Lack of SRAM scaling compared to N5according to analysts from chinese renaissance.
“N3E has six fewer EUV layers than the baseline N3, resulting in less density increase but simpler process complexity, intrinsic cost and manufacturing cycle time,” said China Renaissance. Analyst Szeho Ng wrote in a note to clients this week.
| Advertised PPA improvements for new process technology Data presented in conference calls, events, press briefings and press releases |
|||
| TSMC | |||
| N3 versus N5 |
N3E versus N5 |
||
| Power | -25-30% | -34% | |
| performance | +10-15% | +18% | |
| logic area
Discount* % Logic density* |
0.58 times
-42% 1.7 times |
0.625x
-37.5% 1.6 times |
|
| SRAM cell size | 0.0199µm² (-5% vs N5) | 0.021µm² (same as N5) | |
| Volume manufacturing industry |
Late 2022 | Second half of 2023 | |
According to Ho, TSMC’s original N3 features up to 25 EUV layers, some of which can be multi-patterned to increase density. Under the agreement, N3E will support up to 19 EUV layers and use only single-patterning EUV, resulting in less complexity but also lower density.
“Client interest in optimized N3E (mainly limited to Apple after baseline N3B ramp-up) is strong, with HPC (AMD, Intel), mobile (Qualcomm, Mediatek), and ASIC (Broadcom) It employs computationally intensive applications (e.g., Marvell),” wrote Ho.
It looks like N3E will be TSMC’s main 3nm-class working horse before N3P, N3S, and N3X come later.
Hundreds of billions of N3
TSMC’s 3nm-class node is set to bring the company just over $4 billion in profits in 2023, but the company is spending tens of billions of dollars to expand its fab capacity to produce chips at various N3 nodes. are going to spend The company’s capital spending this year is expected to be between $32 billion and $36 billion. 70% of that total is for advanced process technology (N7 and below). This includes his N3 capable capacity in Taiwan and his Fab 21 (N4, N5 nodes) installations in Arizona. On the other hand, 20% goes to fabs that make chips in specialized technologies (which essentially means various 28nm-class processes), and 10% goes to things like advanced packaging and mask making.
Spending at least $22 billion on N3 and N5 capacity shows that TSMC is confident in the demand for these nodes. There are good reasons for this. His N3 family of process technologies is set to be TSMC’s last FinFET-based production node family for complex high-performance chips. The company’s N2 (2nm class) fabrication process relies on nanosheet-based all-around gate field effect transistors (GAAFETs). In fact, China Renaissance analyst Szeho Ng said a good portion of his CapEx set for advanced technology this year was spent on his N3’s capacity, with N3E, N3P, N3X, and his N3S. We believe that the foundation for the rollout of N3-capable fabs can also produce chips on the N5 process, so TSMC can take advantage of this capacity if N5-based chips are also in high demand.
“TSMC led 2023 CapEx to $32-36 billion (2022: $36.3 billion), with its expansion focused on N3 at Fab 18 (Tainan),” the analyst wrote in a note to clients. ing.
TSMC’s N2 process technology will launch in 2026, so N3 will indeed be a long-term node for the company. Additionally, this will be the last of his FinFET-based nodes for advanced chips, so not all applications will need his GAAFETs, so they will be in use for years to come. .
