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TSMC Forms 3DFabric Alliance to Accelerate Development of 2.5D & 3D Chiplet Products

Today, most high-end processors are monolithic, but as the cost of using state-of-the-art manufacturing techniques increases, design methodologies are slowly but surely shifting to multi-chiplet modules. In the next few years, multi-chiplet system-in-package (SiP) is expected to become more prevalent, and his advanced 2.5D and 3D chip packaging technology will gain importance. To accelerate and simplify the development of 3D designs, TSMC this week is 3D Fabric Alliance.

Multi-chiplet SiP promises to simplify the development and verification of highly complex designs, but 3D packaging presents many new challenges, requiring entirely new development methodologies. This includes new design flows, new methods of power delivery, new packaging techniques, and new test techniques required for 3D integration. To take full advantage of TSMC’s 2.5D and 3D packaging technologies (InFO, CoWoS, and SoIC), the chip development industry needs the entire ecosystem to work together on chiplet packaging. This is the purpose of the 3DFabric Alliance. conduct.

“3D silicon stacking and advanced packaging technologies open the door to a new era of chip- and system-level innovation. We also need large-scale ecosystem collaboration to help us.” Dr. LC Lu, TSMC Fellow and Vice President of Design and Technology Platforms.

TSMC’s 3DFabric Alliance brings together developers of electronic design automation (EDA) tools, intellectual property providers, contract chip designers, memory manufacturers, advanced substrate manufacturers, semiconductor assembly and test companies, and equipment used for test and verification. unites groups that manufacture The Alliance currently has 19 members, but is expected to expand over time as new members join the group.

As the Alliance leader, TSMC sets certain ground rules and standards. Meanwhile, members of the 3DFabric Alliance will co-define and co-develop some of the specifications for TSMC’s 3DFabric technology, gain early access to TSMC’s 3DFabric roadmap and specifications, and share their plans with those of the foundries and others in the Alliance. can match the plans of the members of , will be able to design and optimize solutions compatible with new packaging methods.

Ultimately, TSMC will be able to provide customers with compatible and interoperable solutions that enable members of the 3DFabric Alliance to rapidly develop and validate multi-chiplet SiPs using 2.5D and 3D packages. I want to be like you.

For example, TSMC developed the 3Dblox standard to unify the design ecosystem with certified EDA tools and flows. 3Dblox features 2.5D and 3D packaging techniques (such as chiplet and interface definition), including physical implementation, power consumption, heat dissipation, electromigration IR drop (EMIR), and timing/physical verification Covers various aspects of building multi-chiplet devices. .

“Through the collective leadership of TSMC and our ecosystem partners, our 3DFabric Alliance provides an easy and flexible way for customers to unlock the power of 3D IC in their designs. I can’t wait to see the innovations we can make,” Lu added.

Ultimately, TSMC envisions the partnership to greatly simplify and streamline the process of developing more advanced chips, especially for small businesses that rely heavily on external IP/designs. For example, if you want to develop a SiP that stacks logical chiplets and connects them to an HBM3-based memory subsystem, you can use EDA software from Ansys Cadence, Synopsys, and Siemens to design compatible chiplets, and IP providers can design them. for sale. TSMC will make the silicon, the memory makers will supply compatible HBM3 KGSDs (known good stacked dies), and Ase Technology will assemble everything. On the other hand, a company that doesn’t have its own engineers can order the design of his entire SiP (or individual chiplets) through Alchip or GUC and, if necessary, build a product over time without having to redesign everything. can be updated. Built according to 3DFabric and 3Dblox standards.

3Dblox is currently supported by four major EDA developers. Ultimately, if an alliance is necessary, all members will support it.

While big companies such as AMD and Nvidia tend to develop their own IP, interconnects, and packaging technologies, multi-chiplet SiPs allow smaller companies to develop complex chiplet-style processors. I promise to For them, standard third-party IP, fast time-to-market, and proper integration are key to success, so the 3DFabric Alliance and what it brings is essential for them.

sauce: TSMC

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