TSMC Might Cut 3nm Prices to Lure AMD, Nvidia
TSMC’s N3 (3nm class) family manufacturing process offers many advantages in terms of performance and power, but the very high cost of the foundry’s initial N3 nodes has hindered widespread adoption. Unsurprisingly, the company is rumored to be preparing to lower its 3nm production estimates in order to spur interest from chip designers. my driver.
TSMC’s published N3 quotes and prices at the moment should be considered rumors, but TSMC’s manufacturing cost on the N3E process could be lower than it was on the first N3. It remains to be seen how much the company will charge for production on other N3 class nodes such as N3P, N3S and N3X. Lowering the price of 3nm production could attract more customers to these nodes, but this won’t happen overnight.
TSMC’s initial N3 manufacturing technology (also known as N3B) is rumored to be exclusively used by Apple. Because Apple is the foundry’s largest customer and is willing to be the first to adopt cutting-edge nodes. However, N3 is an expensive technology to use. N3 uses extreme ultraviolet (EUV) lithography extensively, up to 25 layers, according to the company. chinese renaissance, and depending on the configuration, each EUV scanner currently costs between $150 million and $200 million. To depreciate a fab with such production tools, TSMC should charge more for the production of his N3 process and its successors.
Some say TSMC could charge $20,000 per N3 wafer ($16,000 per N5 wafer). Such estimates depend on many factors, but the key point is that chips are becoming more expensive to produce. For companies like AMD, Broadcom, MediaTek, Nvidia, and Qualcomm, higher costs mean lower profits. As such, chip developers are rethinking how to create advanced designs and use cutting-edge nodes.
“We believe in meaningful [N3] A ramp-up will occur in the second half of 2023 when the optimized version, N3E, will be ready,” wrote Szeho Ng, an analyst at China Renaissance. MTK) and his ASICs (i.e. MRVL, AVGO, GUC) will likely stay in his N4/5 and choose N3E as his first N3 class foray. On the other hand, we believe Baseline’s adoption of his N3 (aka N3B) will be largely limited to Apple products. ”
To stimulate partners to use N3 class process technology, TSMC is reportedly considering lowering its estimates for these nodes. In particular, TSMC’s N3E process, which he uses EUV only up to 19 layers, has a slightly lower manufacturing complexity, thus lower cost of use. TSMC can lower its N3E production estimates without hurting profitability. N3E has no advantage over he N5 when it comes to scaling SRAM cells. This means a larger die size when compared to those made with N3/N3B.
AMD has publicly announced that it plans to use N3 nodes for some of its Zen 5 based designs due in 2024. Nvidia has its next-generation Blackwell architecture coming around the same timeframe. We plan to adopt N3 as the base GPU. Due to the high cost, it is expected that the adoption of N3 class nodes will be limited to certain products. So lowering the estimates will force chip designers to rethink their adoption strategies.
Another problem with TSMC’s N3 is its low yield. Some estimated yields are between 60% and 80%, Digi Times (via Dan Neystedt) indicates less than 50%. That said, Apple is the only company reportedly using this manufacturing technique, and the company is known to be very secretive, so details regarding early N3 chip yields are out. It should be taken in coarse grains of salt.