TSMC Readies N2P and N2X: 2nm with Enhanced Performance
At the 2023 North American Technology Symposium TSMC clearly Detailed information on the upcoming 2nm-class process technology, which is expected to be production ready in 2025-2026. Increase transistor density. Additionally, TSMC is planning his N2X, a node designed to offer maximum performance and support higher voltages.
N2 offers the benefits of the entire node
TSMC’s proprietary N2 process technology, scheduled to enter volume production in 2025, introduces gate-all-around (GAA) nanosheet transistors. Compared to N3E, the new node promises 10% to 15% better performance at the same power and transistor count, or 25% to 30% lower power consumption while maintaining the same frequency and complexity. increase. As for scaling, TSMC refrained from providing detailed numbers, but said that the new manufacturing technique could increase chip density by 15%. , and 20% analog circuitry.
TSMC’s N2 progress appears to be on schedule. At the symposium, TSMC announced that the performance of Nanosheet GAA transistors reached more than 80% of his target specification, and the average yield of 256Mb SRAM test ICs exceeded 50%.
N2P: Backside Power Rail for High Performance Efficiency
N2 offers distinct advantages over N3E, but its successor, N2P, is even more impressive. TSMC’s second-generation 2nm-class process is designed to improve transistor performance, reduce power consumption, increase transistor density, and eliminate the risk of interference between data and power wires within the chip. Configured to incorporate a backside power delivery network (PDN).
Back-end-of-line (BEOL) and contact resistance have been major challenges for chip makers for some time, so backside power delivery is one of the most important innovations in recent years. By relocating the power rails to the backside of the wafer, the backside power supply separates the I/O and power traces, alleviating high via resistance issues at BEOL.
TSMC doesn’t provide specific numbers on the performance, power, and area (PPA) benefits of N2P over N2, but some analysts believe the backside PDN is a single-digit reduction in power consumption and a double-digit said it could lead to an increase in transistor density in Bearing in mind that TSMC will likely optimize his N2P further, we expect the technology to be much more advanced than N2 and N3 in terms of both performance efficiency and transistor density. .
TSMC expects N2P to be ready for high volume production (HVM) in 2026, so we expect the actual chips manufactured at this node to ship in 2027. In 2024 he will be 2-3 years ahead of TSMC with RibbonFET GAA transistors and PowerVia backside PDN) and backside power rails.
N2X: High Voltage for Ultimate Performance
TSMC develops N2X, a manufacturing process tuned for high-performance computing (HPC) applications such as high-end data center CPUs. In general, these chips are power hungry and need the ability to clock up at peak times. This means that they must be able to handle high voltages and high currents. Since this node is expected to be available as early as 2026, TSMC is not currently outlining performance enhancements to N2, N2P, and N3X. On the other hand, as with all modern manufacturing techniques, maximum performance and efficiency can only be achieved through extensive design engineering co-optimization (DTCO) between the foundry and his IP developers.