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TSMC Readies N2P and N2X: 2nm with Enhanced Performance

At the 2023 North American Technology Symposium TSMC clearly Detailed information on the upcoming 2nm-class process technology, which is expected to be production ready in 2025-2026. Increase transistor density. Additionally, TSMC is planning his N2X, a node designed to offer maximum performance and support higher voltages.

(Image credit: TSMC)

N2 offers the benefits of the entire node

TSMC’s proprietary N2 process technology, scheduled to enter volume production in 2025, introduces gate-all-around (GAA) nanosheet transistors. Compared to N3E, the new node promises 10% to 15% better performance at the same power and transistor count, or 25% to 30% lower power consumption while maintaining the same frequency and complexity. increase. As for scaling, TSMC refrained from providing detailed numbers, but said that the new manufacturing technique could increase chip density by 15%. , and 20% analog circuitry.

(Image credit: TSMC)

TSMC’s N2 progress appears to be on schedule. At the symposium, TSMC announced that the performance of Nanosheet GAA transistors reached more than 80% of his target specification, and the average yield of 256Mb SRAM test ICs exceeded 50%.

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