Alpha Wave says it has Tape out one of the industry’s first chips (opens in new tab) It is the second generation of the 3nm class process node created using TSMC’s N3E manufacturing technology. The chip is manufactured by TSMC (Taiwan Semiconductor Manufacturing Co.) and has passed all the required tests. This will be demonstrated at his OIP forum at TSMC later this week.
The chip in question is Alphawave IP zeus coreThe 100 1-112Gbps NRZ/PAM4 Serializer/Deserializer (SerDes) supports a number of standards that are expected to spread in the next few years. This includes 800G Ethernet, OIF 112G-CEI, PCIe 6.0 and CXL3.0. SerDes are said to support very long channels to enable flexible connectivity solutions for next-generation servers.
Alphawave President and CEO Tony Pialis said: “Our partnership continues to bring innovative high-speed connectivity technologies that power state-of-the-art data centers, and we are pleased to showcase these solutions at the TSMC OIP Forum event.”
| N3E vs N5 | N3 vs N5 | |
| More Speed @ Same Power | +18% | +10% ~ 15% |
| Power Reduction @ Same Speed | -34% | -25% ~ -30% |
| logic density | 1.7 times | 1.6 times |
| HVM start | Q2/Q3 2023 | Second half of 2022 |
TSMC plans to introduce five 3nm-class process technologies over the next two to three years. The 1st gen vanilla N3 node is expected to be used for some designs by TSMC’s alpha customer (read: Apple), while the 2nd gen his N3E will feature an improved process window. . and low output.
N3E is expected to see significantly more widespread adoption than the regular N3, but in mid-2023 or 3rd 2023, about a year after TSMC begins mass production (HVM) using its N3 production node. Mass production is expected to begin in the quarter.
Like all serializer/deserializer chips, Alphawave IP’s SerDes are relatively small pieces of silicon that can utilize state-of-the-art process technology. Such designs can be used as “pipe cleaners” to learn the characteristics of manufacturing nodes. For that reason, it makes perfect sense for Alphawave to build the ZeusCORE100 in his TSMC’s N3E process.
After TSMC launches N3E HVM next year, it will launch 3 more, including the performance-oriented N3P, the N3S manufacturing technology for chips requiring high transistor density, and the N3X manufacturing process for performance-demanding applications such as microprocessors. We plan to offer two 3nm class nodes.
