Gaming PC

AMD Details EPYC Bergamo CPUs With 128 Zen 4C Cores, Available Now

(Image credit: Forbes)

AMD announced a range of new products today at its Data Center and AI Technology Premier Event in San Francisco, California. The company has finally released details about its 5nm EPYC Bergamo processors for cloud-native applications and the chips are shipping to customers now.

AMD also has an Instinct MI300 processor with 3D-stacked CPU and GPU cores on the same package as the HBM and eight accelerators in one platform delivering a staggering 1.5TB capacity. They also announced a new GPU-only MI300X model that will be used. HBM3 memory. AMD also announced EPYC Genoa-X processors with up to 1.1GB of L3 cache. All three of his products are available now, but AMD will also launch his EPYC Sienna processors for carriers and edge later in 2023.

AMD EPYC Bergamo

AMD’s 128-core EPYC Bergamo processor is the industry’s first x86 native CPU, designed for highest core density with optimized Zen 4c cores that take half the space required for each core It has been. These chips will compete with Intel’s 144-core Sierra Forest chips, which mark the debut of Efficiency Cores (E-cores) in Intel’s Xeon data center lineup, and Amper’s 192-core AmpereOne processors, not to mention custom silicon in development. . Adopted by Google and Microsoft.

All of these products are designed to maximize power efficiency for highly parallel, latency-tolerant workloads. Examples include high-density VM deployments, data analytics, and front-end web services. The chip offers a higher core count than standard data center solutions and a lower frequency and power envelope.

AMD’s Bergamo features 128 cores and will be in a server platform utilizing the same socket SP5 as the standard 96-core EPYC Genoa processor. Like its regular counterpart, Bergamo supports 12-channel memory running at DDR5-4800. AMD forged the chip by combining a chiplet with Zen 4c cores with the company’s existing “Floyd” central I/O die, making the computing chiplet a memory and I/O chip based on an older process node. Tie to let.

Swipe to scroll horizontally
row 0 – cell 0 cores/max threads Base/Boost (GHz) Default TDP L3 cache
9754 128/256 2.25/3.1 360W 256MB
9754S 128 / 128 2.25/3.1 360W 256MB
9734 112/224 2.2/3.0 320W 256MB

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