During Computex 2023, I had the chance to visit AMD’s towering offices in Taipei, Taiwan, see the company’s Ryzen AI demo, and speak with David McAfee, Corporate VP and GM of Client Channel Business. . While most of our conversation centered around AMD’s efforts in the consumer AI space, I also jammed in some questions about his take on AMD’s view on hybrid CPUs. McAfee said AMD has a different vision than Intel when it comes to hybrid processors and can avoid the complications that forced Intel to remove his AVX-512 support from its chips.
I interviewed AMD CTO Mark Papermaster two weeks ago in Antwerp, Belgium. He told me that future AMD clients will have “a mix of high-performance cores and power-efficient cores for speed.” [consumer] This suggests that AMD will adopt a hybrid CPU execution core design in the future, similar to Intel before. It wasn’t all that surprising. We saw the first indications of two different CPU core types in AMD’s software manuals a few months ago. Additionally, AMD is already laying the groundwork with its upcoming EPYC Bergamo chips which will feature high-density Zen 4c cores similar to efficiency cores.
AMD’s current Ryzen 7040 laptop chips already feature a hybrid design but without two different types of CPU cores. Instead, the Ryzen 7040 features only one type of CPU core combined with a built-in AI accelerator engine that works independently of the CPU and GPU cores. This engine benefits certain types of AI inference workloads, while CPU and GPU cores outperform other types of inference. Therefore, it is important to distribute different AI workloads to the correct type of cores to get the best performance and power efficiency.
Throwing separate performance and efficiency CPU cores into that combination introduces yet another computational option for AI inference workloads. I have McAfee, conceptually, a dedicated silicon (AI engine). McAfee explained that the AI engine’s strict focus on his AI-specific operations makes it more efficient than general-purpose CPU computing (even efficiency cores).
We then moved on to discuss Intel’s hybrid chips. This hybrid chip has two types of cores, each with its own microarchitecture. This created an interesting problem. Intel’s performance cores support AVX-512, but smaller efficiency cores do not. This led Intel to completely (eventually forcefully) disable his AVX-512 support, thus disabling the functionality of their own chips and wasting valuable die area. became.
I asked McAfee how he felt about AMD’s approach to hybrid design.
“I would say that the way we think about this, the approach of using two very different performance and efficiency cores with very different ISA support, IPC and features, is not necessarily It’s just not the right approach,” McAfee replied. “I think it gets a lot more complicated as to what can be done where.
“As we develop this further over time, I think we will see that it is an approach that considers the benefits that different core targeting can offer, but from an application perspective, it goes way beyond that. It’s going to do that, it’s much more homogenous.”
We already know that AMD’s Zen 4C efficiency cores that will be used in the upcoming Bergamo server chips will support the same instructions (like AVX-512) as the full-featured performance cores. However, the cache hierarchy is reduced to reduce die area consumption. The goal is that both core types have the same IPC for performance and efficiency cores. In contrast, Intel’s efficiency cores have lower his IPCs than performance cores (which may come at a trade-off with the goals of other e-cores such as Sierra Forest).
“ISA first provides a dramatic advantage by ensuring that workloads are consistent enough to run on any core,” McAfee said. “And even if you look at today’s Ryzen desktop CPUs, how the Windows scheduler works, the ability to identify faster cores, slower cores, etc. and direct threads to different cores depending on their ranking and function within the system. CPU: This is an established technology that we’ve been using for quite some time, and we believe this will force the core functionality to use a more consistent mechanism.
“This is a much more tried and true way to look at incorporating multiple different core targeting types into your design. I think Intel’s approach introduces a lot of complexity into how it works. And I think our analysis went something like that: don’t think we’re going the same way as them when it comes to Ryzen processors,” McAfee concluded.
Contrary to Papermaster’s comment, McAfee declined to say if or when hybrids would be introduced to Ryzen, suggesting that AMD will not be making any claims, whether it’s a monolithic APU or one of its chiplet-based models. I’m not sure where Ryzen will first introduce a hybrid architecture. However, it’s clear that AMD envisions a hybrid future that avoids the trade-offs seen in Intel’s design decisions behind Alder and Raptor Lake processors.
Some of AMD’s own decisions may have come from analyzing Intel’s failures, or it may have been common sense to reuse IP in existing core architectures. It’s much easier to fine-tune the microarchitecture than to start with a blank design. In any case, unless Intel follows suit, the ability to maintain AVX-512 support will give AMD a performance advantage in vectorized workloads.
Conversely, some argue that Intel’s approach of having separate microarchitectures tuned for low-power operation is the better approach, even when combined with uniform ISA support across both types of cores. If Intel fixes the ISA mismatch with Meteor Lake and keeps AVX-512 support across both core types, it could be a strong combo too.
In either case, AMD will be the second to market with a hybrid design, but it’s clear they’ll take a very different approach. Only time will tell how the two techniques stack up in the benchmark.
