AMD officials revealed something unexpected during the company’s Meet the Experts webinar today. This puts persistent memory devices such as SSDs on the memory bus for better performance. By putting remote memory devices into the same pool as system DRAM, CXL provides improved performance, lower latency, and memory expansion capabilities. Think he can expand memory by plugging an SSD or better memory into any device that plugs into a PCIe or m.2 port.
Unlike Optane, which was discontinued by Intel due to poor adoption, CXL already enjoys broad industry support through its open protocol. In fact, AMD and Intel, along with many other companies, are working on the new specification.
The Meet the Experts show covered a variety of topics including AMD’s AM5 platform, DDR5 memory, and PCIe 5.0 SSDs. The moderator then conducted a question and answer session. Storage When asked why her devices aren’t attached to the memory bus, Leah Schoeb, senior her developer manager at AMD, said that persistent memory (such as SSDs) and memory are now different protocols and I explained that communication was blocked because I was communicating.
“[…]It’s not that we won’t bridge that communication in the future. This is something we are looking at with technologies like CXL. So over the next three to five years, we’ll see it first in the server realm, but then we’ll see it move into the client realm. [consumer] It’s a way to ensure that memory and storage can communicate on the same bus through CXL. “
The moderator asked Chris Ramseyer, senior manager of technical marketing at Phison, if this topic should be added.
“Well, to be honest, I’m on the phone about this. Some of them are with Leah. I don’t know how much I can really give. I haven’t announced anything in this area.” Hmm, but I can say that it’s a work in progress.Also, this will be another ecosystem type project.It’s not just Phison or AMD that puts this together. All of us need to work together to do this.These collaborations have really advanced the PC over the past few years, and we’re looking forward to doing it to advance technology and performance, energy efficiency, and more. I look forward to it,” he commented.
The CXL specification is an open industry standard that provides a cache coherent interconnect between CPUs and accelerators such as GPUs, smart I/O devices such as DPUs, and various types of DDR4/DDR5 and persistent memory. Interconnection allows the CPU to operate in the same memory space as the connected devices, improving performance and power efficiency while reducing software complexity and data movement.
However, for the protocol to work, both the host CPU and the connected devices (memory, persistent memory, GPUs, accelerators, etc.) require dedicated silicon. To do that, the functionality has to be built into the chip, and like any new technology, CXL will take time to mature.
However, the first CXL capable processors are coming soon. Intel’s Sapphire Rapids and AMD’s EPYC Genoa will come with early revisions of the specification built around the PCIe 5.0 interface. A new revision of the CXL specification, still in development, will support PCIe 6.0 and more advanced features such as memory sharing and pooling. AMD announces EPYC Genoa server chips November 10 live broadcastSapphire Rapids is expected to arrive early next year, so CXL technology is at the apex of real-world use.
AMD’s disclosure today doesn’t give a specific date or chip generation for CXL support on its consumer CPUs, but the mentioned 3-5 year window is set to debut in the 2024 timeframe. It suggests that you can see it after PCIe 6.0 devices.
