At its 2023 Technology Symposium, TSMC revealed additional details about its upcoming N4X technology designed specifically for high-performance computing (HPC) applications. This node promises ultra-high performance and increased efficiency while maintaining IP compatibility with N4P (4 nm class) process technology.
Yujun Li, Business Development Director for TSMC Foundry’s High Performance Computing Business Unit, said, “N4X is a great example of how we can drive extreme performance while minimizing leakage power penalties. It really sets a new benchmark.”
TSMC’s N4X technology belongs to the company’s N5 (5nm class) family but has been enhanced in several ways and optimized for voltages above 1.2V in overdrive mode.
To achieve higher performance and efficiency, TSMC’s N4X improves transistor design in three key areas. First, we improved the transistor to improve both processing speed and drive current. Second, the foundry incorporated new high-density metal-insulator-metal (MiM) capacitors to provide reliable power even under high workloads. Finally, I modified the backend metal stack to provide more power to the transistors.
Specifically, N4X includes the N4P device offering plus Ultra Low Voltage Transistors (uLVT) for applications requiring very high efficiency and Ultra Low Threshold Voltage Transistors (eLVT) for applications requiring high efficiency Add four new devices. Runs at high clock. For example, N4X uLVT with Overdrive provides 21% lower power at the same speed compared to N4P eLVT, while N4X eLVT with OD has 6% faster critical path speed compared to N4P eLVT is.
| Advertise PPA improvements for new process technology Data presented during conference calls, events, press briefings and press releases |
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| TSMC | ||||||||||
| N5 versus N7 |
N5P versus N5 |
N5 HPC versus N5 |
N4 versus N5 |
N4P versus N5 |
N4P versus N4 |
N4X versus N5 |
N4X versus N4P |
N3 versus N5 |
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| Power | -30% | -Ten% | ? | low | -twenty two% | – | ? | ? | -25-30% | |
| performance | +15% | +5% | +7% | taller than | +11% | +6% | +15% again more |
+4% that’s all |
+10-15% | |
| logic area
Discount % (density) |
0.55 times
-45% (1.8 times) |
– |
– |
0.94 times
-6% 1.06 times |
0.94 times
-6% 1.06 times |
– |
? |
? |
0.58 times
-42% (1.7 times) |
|
| Volume manufacturing industry |
Q2 2020 | 2021 | Q2 2022 | 2022 | 2023 | Second half of 2022 | H1 2024? |
First half of 2024? | Second half of 2022 | |
The N4X offers significant performance improvements over the N4 and N4P, but still uses the same SRAM, standard I/O, and other IP as the N4P, making it easier and cost-effective for chip designers to design. Well migrated to N4X. On the other hand, bearing in mind his IP compatibility of the N4X and N4P, it is logical to expect the N4X’s transistor density to roughly match that of his N4P. Although focused on this technology, chip designers expect to use it for ultimate performance, not maximum transistor density or small chip dimensions.
TSMC claims that N4X has achieved performance targets for SPICE models, so customers can start using the technology today in HPC designs that are scheduled to go into production next year.
For TSMC, N4X is a key technology, as HPC design is expected to be the company’s main revenue growth driver over the next few years. The chip contract maker said in 2030 he expects HPC to account for 40% of his revenue, followed by smartphone (30%) and automotive (15%) applications. I’m here.
