Intel published nine research papers IEDM 2022 The company aims to deliver on its promise to develop processors with more than 1 trillion transistors by 2030, laying the foundation for future chip designs.
The work includes new 2D materials for transistors, new 3D packaging techniques that narrow the performance and power gap between chiplet and single-die processors to an almost imperceptible extent, and “remember when power is removed.” ” transistors, embedded memory. It can be stacked directly on top of transistors and can store multiple bits per cell.
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Intel’s Component Research (CR) group lays the initial foundation for the company’s future technologies, but not all of these initiatives lead to marketable products. Those that hit the market usually arrive in 5 to 10 years.
The group has an impressive track record of already-market innovations such as FinFET, strained silicon and Hi-K metal gates that have revolutionized transistor design across industries. Intel already has several other technologies on the roadmap, including RibbonFET Gate All Around (GAA) transistors, PowerVia backside power delivery, EMIB and Foveros Direct. All of these came out of this research group.
The group submitted nine research papers at this year’s international conference. 68th Annual IEEE International Electronic Devices Conference, and below some of them are described in a little more detail. However, Intel has yet to present a paper at the conference, so this covers a wide range of topics.
Although the pace of increase in transistor density is roughly in line with Moore’s Law, the economics of today’s chips have not improved at the same pace. The price per transistor is increasing as we move to higher density nodes. Furthermore, the problem is compounded by the poor scaling of some chip elements such as analog and cache. As such, the industry is moving en masse to chiplet-based designs for high performance chips.
The overarching goal of chiplet-based designs is to reduce the power consumption and performance (latency, bandwidth) of data paths within single-die monolithic processors while exploiting the economic benefits of using chiplet-based approaches. Maintaining the best attributes. For example, higher yields from smaller dies fabbed on leading-edge processes, or the ability to use older, cheaper nodes for some of the other features that don’t see much density gains.
Thus, the battlefield for semiconductor supremacy has shifted from transistor speed to interconnect performance, with new technologies such as silicon interposers (EMIB) and hybrid bonding technology at the forefront to improve economics. has appeared in
However, these approaches still result in inevitable performance, power, and cost trade-offs that Intel’s new “Quasi-Monolithic Chips” (QMC) 3D packaging technology is addressing. As the name suggests, Intel’s QMC aims to provide nearly the same characteristics as an interconnect built directly onto a single die.
QMC is a new hybrid bonding technology featuring a sub-3 micron pitch that offers a 10x improvement in power efficiency and performance density over the research Intel submitted at last year’s IEDM. A previous paper covered a 10 micron pitch approach, which was already a 10x improvement. Thus, Intel has found a path to a 100x improvement in just a few years. This indicates that the company’s efforts in hybrid bonding are accelerating rapidly. The QMC also allows multiple chiplets to be stacked vertically on top of each other, as shown in the figure above.
This white paper discusses incredible interconnect densities of hundreds of thousands of connections per square millimeter and power consumption (measured in picojoules per bit – Pj/b) comparable to those found in monolithic processors. Outline. Additionally, the new paper outlines several new materials and processes used to fabricate such devices, paving the way for real-world devices.
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Intel’s process roadmap has already slumped from the nanometer scale to the Angstrom scale, and while the node naming convention long ago lost touch with the actual physical measurements of transistors, continued scaling clearly requires a radical new approach. Most of the industry is betting on moving to 2D atomic channels in the future, but like all new technologies, there are many steps to such a fundamental change.
Today’s chip materials such as silicon are composed of three-dimensional crystals. In other words, atoms are bonded in all three dimensions, so there is a fundamental limit to shrinkage. In contrast, 2D materials are attractive. Because all atoms are bonded in one plane, he can build a feature with a thickness of three atoms.
Join Intel’s research on 2D materials that can be used for 3D GAA transistors. As a refresher, the current GAA design consists of stacked horizontal silicon nanosheets, with each nanosheet completely surrounded by a gate. This “gate-all-around” (GAA) technique reduces voltage leakage that prevents transistors from switching off. This is becoming a bigger problem as transistors shrink, even when the gate surrounds the channel on three sides of him, as seen in FinFET transistors.
Intel is currently branding the GAA design as a Ribbon FET, which is expected to arrive in the first half of 2024. However, beyond ribbon FETs, further innovations are needed, and this 2D study of his fits the bill of potential pathways.
The Intel paper describes gate-all-around (GAA) stacked nanosheet structures with channel materials (nansheets/nanoribbons). This structure is only 3 atoms thick and can operate at room temperature with low leakage current.
The thinness of 2D channel materials makes establishing electrical connections to nanoribbons a difficult task, so Intel also modeled the electrical contact topology for 2D materials. This is an important step in understanding the properties of 2D materials and their function, allowing the company to accurately model further advances.
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Memory in all its forms is an integral part of computing, but it consumes a large power budget at both the chip and system level and is also a performance limiting factor.
Intel also performed the world’s first functional demonstration of 3D stacked ferroelectric memory. The most impressive aspect of this technology is the ability to vertically stack ferroelectric trench his capacitors onto the logic die above the transistors. This allows memory to be layered on top of logic elements rather than being placed in its own separate region as seen in other types of embedded memory such as SRAM used for L1 and L2 caches. increase.
Ferroelectric memory also enables functionality similar to that found in NAND flash. In other words, the ability to store multiple bits of data in a structure that can normally store only one bit. In this case, Intel has demonstrated that per trench he can store 4 bits.
Naturally, this approach improves both bandwidth and memory density while reducing latency and enabling much larger and faster on-chip caches.
Intel also shared mixed phase and defect modeling work in ferroelectric hafnia devices, as well as electrical contact modeling for 2D structures. This facilitates Intel’s own research and development process.
Intel is also working on a “remember” transistor. This means that it does not lose data (on/off state) when power is lost. This is similar to non-volatile storage such as NAND, which can retain state when power is removed, but comes in the form of logic transistors. Intel says he has overcome two of the three obstacles to using this technology at room temperature. We are especially looking forward to this presentation.
Other papers from Intel at the event include GaN-on-silicon wafers that will enable future technologies beyond 5G, and storing quantum information to create better qubits for quantum computing. Other areas of research, such as better methods, are outlined.
It’s been 75 years since the transistor changed the course of history. Intel’s Vice President of Technology Development and General His manager, Dr. Ankeleher, will also give a special address at his IEDM on Monday. The “Celebrating his 75th Anniversary of the Transistor! Seeing the Evolution of Moore’s Law Innovation” presentation takes place on Monday, Dec. 5 at 9:45 am PT.