Intel Details PowerVia Backside Power Delivery Technology

Intel on Monday detailed the implementation of the backside power delivery network (BS PDN) that will be part of the Intel 18A and 20A (18/20 Angstrom, 1.8/2.0nm class) manufacturing process. In addition, the company also revealed more information about the benefits that this technology offers to its internal Intel 4+ PowerVia nodes that are specifically designed for the best BS PDNs.

Rear power supply

Intel’s 18A and 20A manufacturing technology introduces two key innovations: the RibbonFET gate-all-around field effect transistor (GAAFET) and the PowerVia rear power delivery network. The benefits of GAA transistors have been discussed previously and are beyond the scope of today’s announcement. Instead, we will focus on the power delivery on the back.

The backside power rail is intended to separate the power and I/O traces and move the power lines to the backside of the wafer. This method addresses issues such as increased via resistance at the back end of line (BEOL), ultimately improving transistor performance and reducing power consumption. It also eliminates possible interference between data and power lines and increases logic transistor density.

Over time, BD PDN will become a standard chip feature, but for now, Intel is blaming it for strained silicon at 90nm in 2003, hafnium-based high-K metal gates at 45nm in 2007, and 22nm in 2012. We see it as a major breakthrough innovation similar to FinFET. .

According to Intel, implementing a backside PDN on a test chip on an internal process node has increased clock speed by more than 6%, reduced IR voltage drop by 30%, and improved cell utilization in large areas of the E-core die. . to over 90%. Despite its advantages, implementing and building a rear power supply is a challenge for several reasons.

Building Power via Rear PDN

Building a backside PDN is very different from a traditional frontside power supply. These days, it’s also pretty easy to manufacture cutting-edge chips. Fabrication of every wafer starts with the most complex M0 transistor layer with pitch as low as 30nm (for Intel 4 node) using the most sophisticated fabrication tools such as EUV scanners. Chip makers then have to build a less complex layer of transistors on top of the first layer, connecting all layers to power all the transistors, so they gradually increase in size. increase.

The actual physical wires for I/O and power look huge compared to the transistor layers, and with each new generation it becomes harder and more expensive to route them properly.

Processing a wafer with chips powered by Intel’s PowerVia BS PDN involves creating all the complex logic layers and signal wires, then flipping the wafer to build the power delivery network “above” the logic. To do. On paper, such an “inversion” doesn’t look like a big deal. However, it adds quite a few process steps, including removing “extra” silicon from the wafer to build his PDN on top of the logic transistors, CMP cleaning, metrology, lithography and etching.

Such process loops don’t require cutting-edge tools in the factory, but they are still expensive. In fact, Intel’s slide shows that Intel 4 process technology uses 15 metallic layers and 1 Redistribution Layer (RDL), while Intel 4 + PowerVia has 14 front layers, 4 rear layers, and It shows that RDL is used and the total number of layers is increased. Up to 18+RDL.

“As before, the transistors are built first, then the interconnect layers are added,” said Ben Sell, vice president of technology development at Intel. “Now for the fun part, flip the wafer and polish everything to expose the bottom layer where the wires are connected. […] Power is connected. We call it silicon technology, but very little silicon remains on these wafers. ”

For the backside PDN, there are several factors to consider. First, the manufacturing process would change significantly, so Intel had to find a way to ensure high yields despite the significant change. Second, Intel needed to make sure the backside PDN was as reliable as his current PDN and works as intended. Third, with I/O and power wires on either side of the transistor, cooling the chip will become increasingly difficult. Fourth, Intel has to remove the backside power interconnect to access the transistor layer, making the chip much more difficult to debug.

Intel’s PowerVia process has another peculiarity. Intel believes that as it removes excess silicon from the backside of the wafer, it loses its rigidity, so it bonds a carrier wafer to the signal side of the wafer to hold the structure together. That carrier wafer will eventually get thinner too, but that addition is also a complex (and possibly necessary) process step.

Another thing about Intel’s PowerVia rear PDN is that the BS PDN doesn’t use embedded power rails, but instead utilizes nanoscale silicon vias (TSVs) to power the transistor layers directly. This is clearly why the company calls its technology his PowerVia.

Testing the backside power delivery network

Intel is no longer the undisputed leader in the chip market with the best process technology, so the company cannot afford to risk a potential point of failure in one of its next-generation nodes. So we made the development process a bit easier by separating the development of the RibbonFET GAA transistor and the PowerVia BS PDN, using the regular PDN to handle the RibbonFET and using the proven FinFET to debug PowerVia. bottom.

To test the PowerVia rear power delivery network, Intel built a special manufacturing process based on the Intel 4-node that uses proven FinFET transistors, but comes with a rear power rail instead of the traditional power rail. increase. This process is rightfully called Intel 4+ PowerVia and is used for one of his test chips, codenamed Blue Sky Creek.

Intel’s Blue Sky Creek test chip uses two dies, each with four energy-efficient cores based on the Crestmont microarchitecture. They are designed to operate at 3 GHz at 1.1 volts. The test vehicle was designed for two purposes only. One is to explore the benefits of PowerVia BS PDN, the other is power generation, PDN reliability, chip, cooling, debugging.

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