Intel Foundry Services has introduced a new 16nm class process technology called Intel 16 to address mobile, RF, IoT, consumer, storage, military, aerospace and government applications. The new technology will complement Intel’s 22nm FFL process, resulting in a cheaper FinFET-based node.
According to a press release from synopsis, cadence digital and Ansis, IFS’ Intel 16 is specially engineered to address a variety of customer applications including RF and analog functions (Wi-Fi, Bluetooth), mmWave, consumer electronics, storage, military, aerospace, and government applications. Designed to 16nm-class technology offers higher transistor density, higher performance, lower power, fewer masks, and simpler back-end design rules compared to the planar production nodes currently used for these applications I promise to
There are hundreds of widely used applications with long lifecycles that rely on mature process technology, especially in areas such as application processors, controllers, analog, consumer electronics, and radios. Many use planar transistor-based process technology because of its cost, simplicity of design, and high yield. Industry pundits generally tend to praise very powerful processors such as AMD’s Instinct MI300 and Nvidia’s H100, but even in industries like artificial intelligence and high-performance computing, they tend to be fairly small and power hungry. A lot of chips with only a few pieces.
In many cases, these mature and emerging applications can continue to benefit from new FinFET-based manufacturing technologies. This is why IFS is currently rolling out Intel 16 process technology while TSMC offers his N12e node.
All three major electronic design automation (EDA) and IP providers — Ansis, Cadenceand synopsis — Already supports Intel 16 process technology with certified software flows and IP. For example, Cadence has ported various IP blocks to Intel 16, including PCIe 5.0. 25G-KR Ethernet Multiprotocol PHY. Multi-protocol PHY for consumer applications supporting standards such as PCIe 3.0 and USB 3.2. Multi-standard PHY for LPDDR5/4/4X memory. His MIPI D-PHY v1.2 for cameras and displays. Synopsys, on the other hand, offers his AI-enabled Synopsys.ai toolset for speeding up chip implementation.
Fabless chip developers can get started with design, verification and simulation tools.
