In addition to today’s disclosure of the Rialto Bridge Accelerator, Intel will use this week’s ISC event to provide a quick update to its next-generation Xeon CPU, Sapphire Rapids, which will ship later this year. 4 while Intel beats the upcoming drumsth Generation Xeon scalable chips haven’t heard anything important about expected performance for some time, especially in the area of HPC. So, prior to its official launch shortly after this year, Intel is finally discussing a bit about the expected performance of the HBM-equipped version of the chip, especially for the HPC / supercomputing crowd.
Intel’s first tile Xeon processor, Sapphire Rapids, is also Intel’s first CPU to offer optional on-chip HBM memory and is called Sapphire Rapids Plus HBM. Adding the 64GB HBM2e makes it a fairly complex and expensive chip, but it also makes it a chip that can access much more memory bandwidth than its predecessor x86 CPUs. As a result, this chip is of particular interest to a subset of the high performance computing community, as it provides an alternative route for workloads that are not suitable for GPUs but still require access to large amounts of memory bandwidth.
As part of today’s ISC presentation, Intel has released two slides containing performance figures for the HBM version of Sapphire Rapids (Sapphire Rapids Plus HBM). The idea here is to show a combination of architectural improvements, especially dedicated accelerator blocks and using 64GB of HBM2e memory to keep them powered enough. The prototype processor is compared to Intel’s Xeon Platinum 8380 (Ice Lake-SP) chip.
Keeping in mind that these will be carefully selected performance numbers, Intel is looking somewhere from twice the speed gains of the WRF weather forecast model and more to more than three times the Clover Leaf Euler equation solver. increase. Both are rather narrow use cases, but they are important use cases for the HPC market segment.
Sapphire Rapids Plus HBM will be released later this year along with other Sapphire Rapids families. According to Intel’s current roadmap, a successor is planned for the 2023 timeframe before the entire HBM-equipped Xeon lineup will be integrated into the Falcon Shores XPU in 2024.
