Unofficial rumors have been circulating for some time that Intel’s upcoming codenamed Meteor Lake processors are set to feature L4 cache. now, New Intel Patent discovered by video cards Indicates that Intel has prepared codenamed Adamantine L4 cache tiles available for some CPUs. This IC may compete with AMD’s 3D V-Cache in certain applications, but the chiplet isn’t just used as a performance booster.
Caches typically serve to improve the performance of the memory subsystem by providing the computational cores with the data they need quickly. However, large caches can store large amounts of data, so there are other use cases.of patent Intel’s Adamantine (or ADM) cache suggests that it can improve communication not only between the CPU and memory, but also between the CPU and the security controller. For example, L4 can be used to improve boot optimization, or to retain data from cache on reset for faster load times.
Windows 10 and Windows 11 load times are still pretty fast on Intel platforms today. However, Intel believes that having memory available at reset will enable the development of faster and more efficient BIOS solutions for modern devices such as car infotainment systems and home robots. Automotive and robotics designs tightly couple SoC security to the firmware phase to ensure platform security. Failure to follow the recommendations will prevent the platform from booting into the OS, reducing the risk of attacks and protecting sensitive blocks critical to cars and robots.
The patent itself doesn’t mention Meteor Lake, but the accompanying image shows a processor with two high-performance Redwood Cove and eight energy-efficient Crestmont cores in a single tile made on the Intel 4 manufacturing process, It clearly shows a graphics chiplet based on Intel’s Gen 12.7. architecture (Xe-LPG), plus SoC tiles containing two Crestmont cores and I/O chiplets interconnected using Intel’s Foveros 3D technology. This description corresponds to that of Intel’s Meteor Lake processors. Adamantine L4 caches, on the other hand, can be used for a wide range of applications beyond Meteor Lake.
Here’s Adamantine’s description from Intel:
Next-generation client SoC architectures may introduce large on-package caches, which will enable new usages. Access times for L4 (such as “Adamantine” or “ADM”) caches can be much shorter than DRAM access times, which are used to improve communication between the host CPU and the Security Controller. Embodiments help protect innovations in boot optimization. High-end silicon with large pre-initialized memory on reset has added value and can lead to increased revenue. Also, by making memory available at reset, it defeats traditional BIOS assumptions and reduces firmware stages (pre-CPU reset stage, IBBL stage, IBB stage, etc.) for a faster and more efficient BIOS solution. Create and Automotive IVI (- vehicle infotainment (e.g. turn on rear view camera within 2 seconds), domestic and industrial robots, etc. Therefore, new market segments are likely to become available.
[0059] Embodiments implement firmware-required phases (e.g., IBBL and /or IBB) and SoC key security recommendations can be tightly coupled. Recommendation. Skipping FSP-M and not doing so will prevent the platform from booting the OS. Such an approach ultimately reduces the attack surface and provides a passive way to protect sensitive functional blocks (Intellectual Property Blocks/IP etc.).
