In addition to numerous solid-state storage announcements in the coming days at the 2022 Flash Memory Summit this week, the show will also be a popular place to discuss I / O and interconnect development. It is becoming. .. Starting things on that front, this afternoon the OpenCAPI and CXL Consortium will announce a joint announcement that the OpenCAPI Standards and Consortium’s assets will be transferred to the CXL Consortium and the two groups will work together. With this integration, CXL will become the leading standard for CPU-to-device interconnection. This is because virtually all major manufacturers endorse the standard, and competing standards have broken out of competition and absorbed by CXL.
OpenCAPI has existed for several years before CXL and was one of the earliest standards for cache coherent CPU interconnects. Backed by AMD, Xilinx, IBM and others, this standard extends IBM’s existing Coherent Accelerator Processor Interface (CAPI) technology, opening it to other areas of the industry and managing it under an industry consortium. I am doing. Over the last six years, the OpenC API usage has been modest, especially in IBM’s POWER9 processor family. Similar to similar CPU-to-device interconnect standards, the OpenC API is basically an application extension in addition to the existing high-speed I / O standards, with cache coherency and high speed (so that CPUs and accelerators can work better together. Low latency) Access mode etc. have been added. Closely despite their physical decomposition.
However, as one of several competing standards tackling this problem, OpenCAPI never caught the attention of the industry. Born of IBM, IBM was IBM’s biggest user at a time when his IBM’s share of the server space was on the decline. And even a growing consortium member such as AMD has skipped over this technology, leveraging its own Infinity Fabric architecture for his CPU/GPU connectivity on AMD servers for example. This left OpenCAPI without a strong following and a large user base to keep things moving forward.
Ultimately, a broad industry desire to consolidate behind a single interconnect standard for both manufacturers and customers brought the interconnect wars to a head. And with Compute Express Link (CXL) quickly becoming the clear winner, the OpenCAPI consortium is becoming the latest interconnect standards body to yield and be absorbed by CXL.
Under the terms of the proposed transaction (pending approval by the required parties), the OpenCAPI Consortium assets and standards will be transferred to the CXL Consortium. This includes all of OpenCAPI’s related technologies, as well as the group’s little-known Open Memory Interface (OMI) standard that allows you to connect DRAM to your system via OpenCAPI’s physical bus. In essence, the CXL Consortium will absorb the OpenC API. While we won’t be continuing development for obvious reasons, this move will likely integrate useful technologies from OpenCAPI into future versions of CXL, strengthening the ecosystem as a whole.
With OpenCAPI sublimated to CXL, the Intel-backed standard remains the dominant interconnect standard and will become the de facto standard for the industry going forward. Competing Gen-Z standards were likewise absorbed into his CXL earlier this year, leaving the CCIX standard behind, whose major proponents have joined his CXL consortium in recent years. So while the first CXL-enabled CPUs haven’t shipped yet, at this point CXL has swept the envelope, so to speak, as the server CPU interconnect standard for everything from accelerator I/O (CXL.io) to memory expansion. It’s the only one left. Via the PCIe bus.
