TSMC has developed a new Chip-On-Wafer-On-Substrate-L (CoWoS-L) technology that enables the construction of very large interposers (called supercarrier interposers), pushing the limits of current system-in. A version is in development. – Take package (SiP) size to an unprecedented level. The next-generation CoWoS technology, which is expected to be certified in 2025, could increase the size of the interposer by up to 6x that of Reticle 6, or up to 3.3x what is currently possible.
The drive towards larger chip sizes is driven by the growing global demand for advanced computing capabilities in applications such as artificial intelligence (AI) and high performance computing (HPC). Major companies like AMD, Intel and Nvidia are meeting this demand by developing highly complex processors such as Nvidia’s H100, which sells for around $30,000 per unit.
To boost the computing power of these processors, these companies are using multi-tile chiplet designs. AMD’s Instinct 250X/MI300 and Intel’s Ponte Vecchio are examples of designs that are large and require very high levels of cooling.
The new version of TSMC’s CoWoS-L technology opens new doors by enabling the building of even larger processors. Considering ASML’s EUV tool theoretical reticle limit of 858mm^2, the size of CoWoS-L technology is huge. With 6 reticles, a SiP size of 5148 mm^2 is possible.
However, such a solution would not only accommodate a significant number of large computational chiplets, but would also require a rather large memory subsystem for such a device. TSMC is talking about his 12 stacks of HBM3/4 memory. For HBM3, this means a memory interface with a bandwidth close to 9.8 TB/s.
However, building such a large-scale SiP is a difficult and costly task. To put it into perspective, NVIDIA’s H100 accelerator is already the size of multiple reticles and costs around $30,000. With this in mind, the cost of larger, more powerful chips developed using CoWoS-L technology will undoubtedly be significantly higher.
Besides the economics of the chip itself, there is another big challenge – cooling. SiPs will be some of the most power hungry HPC chips ever and will require advanced cooling systems to prevent overheating. TSMC is researching on-chip liquid cooling technology and has demonstrated that it can cool silicon packages at power levels up to 2.6 kW. While this could potentially address the cooling requirements of these powerful chips, it introduces another level of complexity and cost to the process.
