TSMC on Thursday “Mass Production and Capacity Expansion Ceremony” at Fab 18 in Southern Taiwan Science Park (STSP). Fab 18 is where the production of chips using the company’s N3 (3nm class) process technology takes place. The foundry says his 3nm chips in high volume have good yields and the family of N3 technologies will serve customers for years to come.
TSMC reportedly started mass production (HVM) on its N3 manufacturing process in early September. By now, the first batch of chips had been manufactured and tested, so a formal announcement about mass production would usually be made on the foundry’s 3nm-class process, which is suitable for mass production. Designed to indicate that the chip is “good”. For TSMC, N3 is the foundry’s last general-purpose node based on his FinFET transistors, a very important family of process technology as it will be the node that will serve customers for at least a decade. In fact, TSMC says it will use N3 and its successor to build HVM’s “product with a market value of his $1.5 trillion within five years.”
Compared to TSMC’s N5 manufacturing technology, the company’s N3 production node delivers 10% to 15% performance improvement (at the same power and transistor count) and consumes 25% to 30% less power (at the same in frequency and complexity). , and increases the logic density by about 1.6 times. The N3, on the other hand, has an SRAM bitcell size of 0.0199 µm^², so it offers little SRAM scaling. This is only 5% smaller than the 0.021 µm^² SRAM bitcell in N5.
|Header Cell – Column 0||N3E vs N5||N3 vs N5|
|More Speed @ Same Power||+18%||+10% ~ 15%|
|Power Reduction @ Same Speed||-34%||-25% ~ -30%|
|logic density||1.7 times||1.6 times|
|HVM start||Q2/Q3 2023||Second half of 2022|
On the other hand, the first iteration of TSMC’s 3nm-class manufacturing process (N3, also known as N3B) is expected to be used by early adopters only for some applications, as the process window is reported to be rather narrow. increase. This can lead to lower yields for certain designs. In fact, according to media reports, most of TSMC’s customers now trade SRAM scaling (i.e. lower transistor density) for better process windows, higher performance, and even lower power consumption. Seeking N3E manufacturing technology. Apparently, the N3E features 0.021 µm^² SRAM bitcells and little to no changes from the N5. This means a larger die size for SRAM-intensive designs (most CPUs, GPUs, and SoCs).
Meanwhile, N3 offers FinFlex to chip designers. This is a powerful way to optimize chip die size and performance/power consumption. FinFlex allows developers to combine different types of standard cells within one of her blocks to precisely optimize performance, power and area. This is especially appreciated by designers of complex systems-on-his-chips who tend to take advantage of both transistor performance and performance. transistor density.
Ultimately, TSMC plans to add more nodes to the N3 family. The latest versions of this process include N3P, which promises improved performance, N3S, which is designed for higher transistor density, and N3X, which has increased voltage and further optimized performance for applications such as CPUs.
Customers are queuing for N3 despite high costs
Rumor has it that almost all of TSMC’s most important customers, including AMD, Apple, Broadcom, Intel, MediaTek, Nvidia, and Qualcomm, are interested in using TSMC’s N3 node, but these chip designers It is difficult to know when each of the Foundry’s 3nm bandwagon and which products to use. Apple is expected to be one of the first clients to adopt TSMC’s N3 for one of its premium SoCs, but we don’t know which SoC it is. AMD, on the other hand, plans to adopt his N3 for some of its Zen 5-based offerings due out in 2024, while Nvidia plans to use its next-generation Blackwell architecture-based GPUs due around the same time. May use his N3.
But using TSMC’s N3 doesn’t come cheap. According to some reports, chip contract makers could charge as much as $20,000 per wafer processed using 3nm-class technology. Of course, TSMC’s pricing depends on many factors such as volume, design, and specs, so take the numbers into consideration.
On the other hand, higher estimates mean fabless chip designers may prefer to reserve TSMC’s cutting-edge nodes for premium products while using proven manufacturing techniques to create more mainstream devices. For example, Apple uses TSMC’s N4 (4nm class) manufacturing process exclusively for the A16 Bionic, which powers the company’s flagship iPhone 16 Pro. By contrast, the company’s iPhone 14 non-Pro continues to rely on the A15 SoC from 2021, made with TSMC’s N5P technology.
fab 18 phase 8
Besides announcing the entry of the N3 process technology into HVM, TSMC also held a topping ceremony for the Fab 18 Phase 8 building. The company uses his Fab 18 to manufacture cutting-edge chips at its N5 and N3 production nodes. Once Fab 18 Phase 8 is equipped with production tools, it will significantly expand TSMC’s production capacity. Its state-of-the-art manufacturing process.