At the IDM conference, Intel shared its process technology roadmap and vision for chip designs that will be available in the next three to four years. As expected, Intel’s next-generation manufacturing processes, Intel 4 and Intel 3, are expected to go into high-volume manufacturing (HVM) in 2023 and 2024, respectively. Additionally, the company’s 20A and 18A production nodes are expected to be ready for his HVM in 2024. This means 18A will be available ahead of schedule. IEEE spectrum (opens in new tab) Suggest.
Intel Technologies from Now to 2025
| node: | Intel 7 | Intel 4 | Intel 3 | Intel 20A | Intel 18A |
|---|---|---|---|---|---|
| situation: | HVM | Ready | Ready in the second half of 2023 | Ready in the first half of 2024 | Ready in the second half of 2024 |
| Notable Products: | Raptor Lake, Sapphire Rapids | meteor lake | Granite Rapids, Sierra Forest | Arrow Lake | Future Lake, Future Rapids, IFS |
Note: Process technology readiness does not mean HVM is started.
Intel 4 ready now, Intel 3 planned for 2H 2023
Next year, Intel will release its 14th Generation Core codenamed Meteor Lake CPUs. This is the first mass-market client processor to feature a multi-chiplet (or multi-tile) design where each chiplet set is created using a different process technology. Intel’s Meteor Lake offering will consist of four tiles: Compute tiles (CPU cores) made using Intel 4 process technology (aka 7nm EUV), possibly made by TSMC using N3 or N5 nodes Printed graphic tiles, SoC tiles, and I/O tiles. Additionally, the tiles are interconnected using Intel’s Foveros 3D technology.
Meteor Lake’s compute tiles are arguably the most exciting part of the package as they will be made with Intel 4 (previously known as 7nm). This is the company’s first production node using extreme ultraviolet (EUV) lithography. According to Intel, the manufacturing process is ready for mass production, but it’s only a few months from now when it will roll out on his HVM for Meteor Lake computing chiplets. Bearing in mind that Intel turned on this compute tile in October 2021, it should come as no surprise that the node is operationally ready at this point. What’s a bit unexpected is that Intel hasn’t confirmed this process technology is used in his Xe-HPC compute GPU tiles at Ponte Vecchio, which was planted two years ago.
Intel will start using EUV about four years after TSMC started producing chips on its N7+ node in Q2 2019. Intel has to ensure that the 4nm class node will perform as expected and offer good yields as it will be the first node. It arrives after a rather ill-fated 10nm process family that didn’t perform as expected early in its lifecycle and cost more than the company wanted a few years ago.
Intel 4 process technology is already joining the Intel 3 fabrication node (3nm class) in 2023-2024 as Intel needs to catch up with rivals Samsung Foundry and TSMC. This process will become manufacturable later. Based on data shared by Intel in 2023. It is used to manufacture Intel’s codenamed Granite Rapids and Sierra Forest processors. These are Intel’s high-profile products. Sierra Forest is expected to be the company’s first data center CPU to use energy-efficient cores, competing with a range of high-core-count Arm-based offerings.
Intel is already working on Xeon ‘Granite Rapids’ samples, so the CPU design seems ready and the node itself is on track for HVM 2024.
“The first steps of Granite Rapids are out of the fab and Intel 3 continues on schedule with good yields.” Said Intel Chief Executive Pat Gelsinger said in the latest earnings call. Both are on track for 2024 with Sierra Forest, the first E-core product to run multiple OSes in configurations that are very healthy and deliver world-class performance per watt. “
Intel’s 18A Moves to 2H 2024
Catching up with TSMC and Samsung is important, but Intel needs to overtake both rivals to regain process technology leadership. This is due in his 2024 when the company announces his 20A (20 Angstroms, or 2nm) node. This node uses a RibbonFET brand gate all-around transistor and a backside power delivery called PowerVia. Intel expects the 20A node to be manufacturable in the first half of his 2024. In 2024, it will be used to create chiplets for the company’s codenamed Arrow Lake processors for client PCs.
Intel’s 20A will be the industry’s first 2nm-class node and will make extensive use of EUV to maximize transistor density, delivering just the right performance boost and power reduction. In 2024, it is set to compete with TSMC’s third generation of his 3nm-class (N3S, N3P) process technology, designed to boost transistor density and performance. It is not yet known how these three nodes will overlap with each other. Still, Intel sets the bar very high for the 20A process as he introduces two major innovations (GAA, BPD) at the same time.
Still, 20A isn’t the most advanced process technology Intel plans to start using by late 2025. The company is also gearing up for his 18A (18 Angstroms, 1.8nm) production node, which promises to further improve PPA (performance, power, area). A benefit to Intel and its Intel Foundry Services customers.
For 18A, Intel originally planned to use EUV tools with 0.55 numerical aperture (NA) optics. This is set to provide a resolution of 8nm (down from 13nm for the currently used 0.33 NA EUV tools). However, ASML’s High-NA EUV equipment will be ready for production only in 2025, while Intel is aiming to have his 18A production ready in the second half of 2025, ahead of rivals.
As it is possible to achieve 8nm resolution at the post 3nm node with multiple patterning using current generation EUV tools (although this will lengthen the production cycle and may impact yield) , Intel is willing to take some additional risks with 18A. Use ASML’s Twinscan NXE:3600D or NXE:3800E to create a chip at this node.
After all, the first 20A and 18A test chips are already taped out.
“At Intel 20A and Intel 18A, the first nodes to benefit from RibbonFet and PowerVia, our first internal test chips and chips from a major potential foundry customer were taped out with silicon working in the fab. ,” said an Intel official. “We are on track to regain leadership in transistor performance and power performance by 2025.”
Joint optimization of system technology
Both the 20A and 18A production nodes make extensive use of EUV tools (and sometimes even high NA EUV tools), making chips produced with these technologies very expensive. Even today’s massive monolithic 4nm and 5nm chips are expensive to develop, verify, and manufacture, making multi-tile designs like Intel’s Ponte Vecchio gaining popularity. At 2nm and 1.8nm, further segmentation of high-performance designs makes sense.
Intel believes this will require an entirely new “outside-in” design approach. Years later, Intel said chip designers would decompose the functionality of a single chip into multiple chiplet designs and manufacture chiplets using the best technology to meet performance, power, and cost goals. I’m assuming it will be possible. Intel calls such an approach System Technology Co-Optimization (STCO). For example, logic scales better than his SRAM, so using different nodes (to optimize cost and performance) to create logic and cache, using technologies like Foveros and EMIB It makes sense to string them together.
Given such an approach, a successful foundry must offer different nodes for different chiplets and competitive packaging technologies. This is why Intel needs to stay ahead of its competitors with the best logic technology (i.e. 20A and 18A) to enable the most profitable part of future multi-tile designs.
