Intel Foundry and Arm to Collaborate on 1.8nm Mobile SoCs
Arm and Intel Foundry Services Wednesday announced Design Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO) for Arm’s mobile IP on Intel 18A manufacturing technology (1.8nm class). This plan will enable Arm and IFS clients to maximize performance, reduce power consumption, and optimize die size for upcoming SoCs containing Arm’s IP.
Under the agreement, Intel Foundry Services and Arm will jointly optimize Arm’s IP and Intel’s 18A manufacturing process to improve the performance, power, area and cost advantages of the new node. The two companies will initially focus on mobile SoC designs, but may eventually expand their cooperation to automotive, aerospace, data centers, Internet of Things, and government applications. As part of the deal, Arm and IFS will develop reference designs and optimized process developer kits for mobile SoCs.
Modern chip manufacturing techniques and processor designs are extremely complex and expensive. To maximize the benefits of each new node for a given design, modern foundries and chip developers are optimizing transistor designs, libraries, standard cells, chip layouts, and interconnects.
When it comes to Intel’s 18A manufacturing process, there are a lot of things that can be optimized at the node and design level to get more PPAC benefits from the node. One of the key innovations of Intel 18A is the use of gate-all-around (GAA) transistors, which Intel calls RibbonFETs. In a GAA transistor, the channel is laid out horizontally and completely surrounded by the gate. These GAA channels are created by epitaxy and selective material removal, allowing designers to fine tune the channel by changing the transistor channel width to improve performance or reduce power consumption. increase. If all works well, such control can reduce transistor leakage and performance variability. This presents a huge opportunity for DTCO.
Another advantage of Intel’s 18A is a backside power delivery network (PDN) called PowerVia. PDNs must be customized for specific designs and process technologies to efficiently deliver power and quickly adapt to the widely varying workload behavior of modern processors. This gives DTCO many opportunities. The client and smartphone SoCs should be optimized for bursty operation, while his SoC in the data center should be optimized for constant heavy loads. This is why it is important that (for now) Intel and Arm only support smartphone SoCs.
“The Intel-Arm collaboration expands the market opportunity for IFS, offering new options and approaches for fabless companies that want to access the power of open system foundries with best-in-class CPU IP and leading-edge process technology. said Intel CEO Pat Gelsinger.
One important thing to note about Intel’s 18A is that this process technology is used to manufacture the chips in various locations where IFS operates around the world. This is an advantage of this manufacturing process as there are fabless chip designers looking for localization of chip production.
“As demands for computing and efficiency become more complex, the industry will have to innovate on many new levels.The collaboration between Arm and Intel has made IFS a key foundry partner for our customers, building on Arm. We will be able to deliver the next generation of products that will change the world,” said Rene Haas, CEO of Arm.