Gaming PC

Intel’s New AVX10 Brings AVX-512 Capabilities to E-Cores

Intel posted a new APX (Advanced performance enhancements) Today also announced the new AVX10 [PDF] This provides integrated support for AVX-512 features in both P-cores and E-cores for the first time. This evolution of the AVX instruction set will help Intel avoid serious problems encountered with the new x86 hybrid architecture found in Alder and Raptor Lake processors.

However, the new AVX10 ISA is not supported on Intel’s current generation CPUs. It will be included in future chips. Intel says AVX10 will be the vector ISA of choice in the future for both consumer and server processors.

Intel AVX10 (Advanced Instruction Extensions 10)

At the most basic level, AVX10 will allow Intel chips with both E and P cores to continue to support AVX-512, but 512-bit instructions can only be executed on P cores. The integrated 256-bit AVX10 instructions, on the other hand, can run on either P-cores or E-cores, so the entire chip can still support AVX-512 functionality.

So Intel doesn’t have to disable support for 512-bit vectors like they did when they disabled AVX-512 on both Alder Lake and Raptor Lake.

(Image source: Intel)

Looking more closely, the AVX10 (Advanced construction Extensions 10) ISA is a superset of AVX-512 and comes with all the features of the AVX-512 ISA for processors with both 256-bit and 512-bit vector register sizes.

The integrated AVX10 ISA includes “new versions of 256-bit instructions with AVX-512 vector instructions with AVX512VL feature flag, 256-bit maximum vector register length, eight 32-bit mask registers and embedded rounding support”, which runs on both P and E cores.

However, E-cores are limited to the maximum vector length of 256 bits for converged AVX10, while P-cores can use 512-bit vectors. This feels similar to Arm’s support for variable vector widths in SVE.

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