A day after Japan’s new rules on the export of some wafer fabrication tools to China came into effect, the People’s Republic issued a statement how displeased it was with the move. A representative from China’s foreign ministry declared that the measures appeared to target China directly and highlighted the potential negative effects, including damage to businesses and disruptions to global supply chains.
China’s foreign ministry spokesman Mao Ning said, “China is deeply regretful and dissatisfied with this move, and has made solemn statements to Japan at various levels.” Nikkei newspaper. “We will closely monitor the impact of regulatory policies and resolutely protect our own interests.”
China urged Japan to focus on common interests between the two countries instead of trying to limit the development of the semiconductor industry.
The Foreign Ministry statement was more diplomatic than the slightly offensive language used by China’s top envoy in the United States last week. The latter promised Beijing would not hesitate to respond to further US sanctions and export controls.
“We will not provoke, but we will not retreat from provocation,” Xie Feng said at the forum, adding that China would undoubtedly respond.
Japan’s new export rules require wafer-fabrication-equipment makers to obtain export licenses from the government before shipping 23 manufacturing tools to Chinese firms.
This list includes all immersion lithography scanners, etchers, tools for chemical wafer polishing, and extreme ultraviolet (EUV) mask testers. Made by 10 companies including Lasertec, Nikon, Screen Holdings and Tokyo Electron, these export control list additions coincide with similar restrictions imposed on China by the United States and the Netherlands in recent quarters.
Specifically, export regulations require companies such as ASML, Applied Materials, and Lam Research to obtain export licenses from their respective governments before shipping Chinese company tools that can manufacture logic chips with non-planar transistors on the 14nm/16nm node and below, 3D NAND chips with 128 layers and above, and DRAM ICs with half-pitch below 18nm.
